Shared memory and message passing are traditional parallel programming models used on multiprocessor system-on-chip environments. Underlying models are traditionally meant for static scenarios where all communicating entities and their intercommunication patterns are known a priori by the software engineer. The systems design following such programming models became complex due to dynamic behavior of applications at runtime. The goal of this work is to incorporate a publish-subscribe programming model to an MPSoC framework to decouple, in the time and space, the application development. The modified MPSoC framework is composed of a FreeRTOS kernel running on homogeneous processing elements distributed into a network-on-chip. The results present reduction around of 2% to 30% in DTW application execution time, and low overhead in memory footprint when comparing the original MPI primitives with the publish-subscribe programming model.

Publish-subscribe programming for a NoC-based multiprocessor system-on-chip

Efficient serialization is a must-have feature in distributed embedded protocol stacks because of the restrained resources available for use in such systems. Although there are many serialization libraries out there, only some of them focus on resource usage, which is of most importance for the embedded domain. Thus, a comparison of serialization libraries considering resource usage is of high relevance for the embedded systems domain. This paper presents an experiment-based comparison of serialization libraries while concentrating on resource usage for a multiprocessor system-on-chip (MPSoC) platform. Results show that MsgPuck library surpasses other libraries for both serialization speed and memory consumption criteria.

https://repositorio.pucrs.br/dspace/bitstream/10923/15215/2/Evaluating_Serialization_for_a_Publish_Subscribe_Based_Middleware_for_MPSoCs.pdf

Evaluating Serialization for a Publish-Subscribe Based Middleware for MPSoCs

Providing quality of service (QoS) for many-core systems with dynamic application admission is challenging due to the high amount of resources to manage and the unpredictability of computation and communication events. Related works propose a self-adaptive QoS mechanism concerned either in communication or computation resources, lacking, however, a comprehensive QoS management of both. Assuming a many-core system with QoS monitoring, runtime circuit-switching establishment, task migration, and a soft real-time task scheduler, this work fills this gap by proposing a novel self-adaptive QoS management. The contribution of this proposal comes with the following features in the QoS management: (i) comprehensiveness, by covering communication and computation resources; (ii) online, adopting the ODA (Observe, Decide, Act) runtime closed-loop adaptation; and (iii) reactive and proactive decisions, by using a dynamic application profile extraction technique, which enables the QoS management to be aware of the profile of running applications, allowing it to take proactive decisions based on a prediction analysis. The proposed QoS management adopts a decentralized organization by partitioning the system in clusters, each one managed by a dedicated processor, making the proposal scalable. Results show that the proactive feature accurately extracts the applications’ profile, and can prevent future QoS violations. The synergy of reactive and proactive decisions was able to sustain QoS, reducing the deadline miss rate by 99.5% with a severe disturbance in communication and computation levels, and avoiding deadline misses up to 70% of system utilization.

/pdf/self-adaptive-qos-management-of-computation-and-4r6uedoxxn.pdf

Self-Adaptive QoS Management of Computation and Communication Resources in Many-Core SoCs

The publish-subscribe programming model has been used successfully in many distributed embedded application domains and has been recently ported to the MPSoC domain. However, the publish-subscribe model requires the element of the broker, which is a single process that manages the communication between nodes; a unique point of failure in the system. This paper presents a lightweight extension of the publish-subscribe model with a fault recovery method for the broker. The results show that the proposed method inserts small memory footprint to the system while providing minimal system downtime during recovery.

/pdf/broker-fault-recovery-for-a-multiprocessor-system-an-chip-4kgtn3qono.pdf

Broker Fault Recovery for a Multiprocessor System-an-Chip Middleware

MPSoCs (systemes multiprocesseurs sur puces) avec des centaines de cœurs sont deja disponibles sur le marche. Selon le ITRS, ces systemes integreront des milliers de cœurs a la fin de la decennie. La definition du cœur, ou chaque tâche sera executee dans le systeme, est une question majeure dans la conception de MPSoCs. Dans la litterature, cette question est definie comme allocation de tâches. La croissance du nombre de cœurs augmente la complexite de l'allocation de tâches. Les principales preoccupations en matiere d'allocation de tâches dans des grands MPSoCs incluent: (i) l'evolutivite; (ii) la charge de travail dynamique; et (iii) la fiabilite. Il est necessaire de distribuer la decision d'allocation de tâches a travers le systeme afin d'assurer l'evolutivite. La charge de travail de grands MPSoCs peut etre dynamique, a savoir, de nouvelles applications peuvent commencer a tout moment, conduisant a differents scenarios d'allocation. Par consequent, il est necessaire d'executer le processus d'allocation a l'execution pour soutenir une charge de travail dynamique. La fiabilite est etroitement liee a la distribution de la charge de travail du systeme. Un desequilibre de charge peut generer des hotspots et autres implications thermiques, ce qui peut entrainer un fonctionnement peu fiable du systeme. Dans de grands MPSoCs, les problemes de fiabilite empirent puisque l'augmentation du nombre de cœurs sur la meme puce augmente la densite de puissance et, par consequent, la temperature du systeme. La litterature presente differentes techniques d'allocation de tâches pour ameliorer la fiabilite du systeme. Cependant, ces techniques utilisent des approches d'allocation centralisees, qui ne sont pas evolutives. Pour repondre a ces trois defis, l'objectif principal de cette These est de proposer et evaluer des heuristiques d'allocation de tâches distribuees et dynamiques en assurant l'evolutivite et une distribution equitable de la charge de travail. Une distribution equitable de la charge de travail et du trafic du NoC (reseau sur puce) augmente la fiabilite du systeme dans le long terme, en raison de la minimisation des regions de hotspot. Pour permettre l'exploration de l'espace de conception de grands MPSoCs, la premiere contribution de cette These se situe dans le cadre d'une modelisation multi-niveaux, qui prend en compte differents modeles et de capacites de debogage qui enrichissent et facilitent la conception des MPSoCs. La simulation de modeles de niveau inferieur (par exemple RTL) genere des parametres de performance utilises pour calibrer des modeles abstraits (sans precision d'horloge). Les modeles abstraits permettent d'explorer des heuristiques d'allocation de tâches dans de grands systemes. La plupart des techniques d'allocation de tâches se focalisent sur l'optimisation du volume de communication, ce qui peut compromettre la fiabilite du systeme, en raison d'une surcharge des processeurs. D'autre part, une heuristique qui optimise seulement la distribution de la charge de travail peut surcharger le NoC et compromettre sa fiabilite. La deuxieme contribution importante de cette These est la proposition d'heuristiques d'allocation de tâches dynamiques et distribuees, qui realisent un compromis entre le volume de communication (liens du NoC) et la distribution de la charge de travail (de l'utilisation des processeurs). Des resultats lies au temps d'execution, au volume de la communication, a la consommation d'energie, aux traces de puissance et a la distribution de la temperature dans les grands MPSoCs (144 processeurs) confirment l'hypothese de compromis. Faire un compromis entre la reduction du volume de communication et une distribution equitable de la charge de travail ameliore le systeme de maniere fiable grâce a la reduction des regions de hotspots, sans compromettre la performance du systeme.

/pdf/exploration-of-runtime-distributed-mapping-techniques-for-4p1dtiax3d.pdf

Exploration of runtime distributed mapping techniques for emerging large scale MPSoCs

With the ever-increasing complexity of both embedded application workloads and multiprocessor platforms grows the demand for efficient mapping heuristics able of allocating several application workloads at runtime. The majority of promoted mapping techniques are bespoke implementations that consider an in-house operating system, which is developed to a particular architecture, restricting its adoption in other platforms. This work proposes a FreeRTOS extension that supports distributed task mapping heuristics, which enables to balance application workloads in multiprocessor architectures at runtime. Promoted extension is validated through a trustworthy number of scenarios considering large scale Cortex-M-based multiprocessor systems executing up to 600 application tasks.

Extending FreeRTOS to support dynamic and distributed mapping in multiprocessor systems

FinFET technology appears as an alternative solution to mitigate short-channel effects in traditional CMOS down-scaled technology. Emerging embedded systems are likely to employ FinFET and dynamic voltage scaling (DVS), aiming to improve system performance and energy-efficiency. This paper claims that the use of DVS increases the susceptibility of FinFET-based SRAM cells to soft errors under radiation effects. To investigate that, a methodology that allows determining the critical charge according to the dynamic behaviour of the temperature as a function of the voltage scaling is used. Obtained results support our claim by showing that both temperature and voltage scaling can increase up to five times the susceptibility of FinFET-based SRAM cells to the occurrence of soft errors.

/pdf/impact-of-dynamic-voltage-scaling-and-thermal-factors-on-2eoy5odc03.pdf

F. R. Rosa

Papers

Extending FreeRTOS to support dynamic and distributed mapping in multiprocessor systems

Impact of dynamic voltage scaling and thermal factors on FinFET-based SRAM reliability