This paper presents an innovative modeling strategy for the construction of efficient and compact surrogate models for the uncertainty quantification of time-domain responses of digital links. The proposed approach relies on a two-step methodology. First, the initial dataset of available training responses is compressed via principal component analysis (PCA). Then, the compressed dataset is used to train compact surrogate models for the reduced PCA variables using advanced techniques for uncertainty quantification and parametric macromodeling. Specifically, in this work sparse polynomial chaos expansion and least-square support-vector machine regression are used, although the proposed methodology is general and applicable to any surrogate modeling strategy. The preliminary compression allows limiting the number and complexity of the surrogate models, thus leading to a substantial improvement in the efficiency. The feasibility and performance of the proposed approach are investigated by means of two digital link designs with 54 and 115 uncertain parameters, respectively.

/pdf/a-data-compression-strategy-for-the-efficient-uncertainty-48wprt740f.pdf

A Data Compression Strategy for the Efficient Uncertainty Quantification of Time-Domain Circuit Responses

The practical approach to implement a 1 Ω current probe with verification for measuring the IC conducted emission is proposed. The 1 Ω/150 Ω direct coupling method is reviewed and the considerations on improving the applicable bandwidth of 1 Ω method are discussed. The critical component, 1 Ω resistor which dominates the frequency response, is designed. The realized 1 Ω probe was fully certified with the specification in the IEC 61967-4 standard. The experimental results show the applicable bandwidth of the 1 Ω could cover 1 GHz with accuracy and confidence.

Investigation on realizing 1 Ω current probe complied with IEC 61967-4 direct coupling method

A novel on-chip measurement technique for characterizing conducted electromagnetic emission of integrated circuits in the gigahertz frequency range is proposed. The International Electrotechnical Commission (IEC) direct coupling method is reviewed, and the considerations on improving the applicable bandwidth of the testing probes are discussed. Design of the most critical resistive components for the probes is elaborated to achieve the required accuracy and bandwidth. With the compact chip probes realized by the integrated passive device (IPD) technology, the measurement bandwidth can be significantly extended compared with the conventionally used surface mounted device resistors. The probes are verified to comply with the IEC 61967-4 standard, and an excellent bandwidth up to 15 GHz can be achieved. By connecting the flipped die under test with the probes embedded in IPD substrate (core sizes of the 1- $\Omega $ current probe and 150- $\Omega $ voltage probe are $0.55~\text {mm}\times 0.77$ mm and $0.83~\text {mm}\times 1.49$ mm, respectively), the conducted emission measurement of a 58-MHz oscillator integrated circuit is demonstrated up to 3 GHz.

Wideband Conducted Electromagnetic Emission Measurements Using IPD Chip Probes

This paper addresses the generation of behavioral models of digital integrated circuits (ICs) for signal and power integrity simulations. The proposed models are obtained by external measurements carried out at the device ports only and by the combined application of specialized state-of-the-art modeling techniques. The present approach exploits a behavioral formulation, leading to models reproducing all the behavior of the IC ports as the input/output buffers and the core power delivery network. The modeling procedure is demonstrated for a commercial nor Flash memory in 90-nm technology housed by a specifically designed test fixture.

Behavioral Modeling of IC Memories From Measured Data

The growing importance of signal integrity (SI) analysis in integrated circuits (ICs), revealed by modern system-in-package methods, is demanding for new models for the IC sub-systems which are both accurate, efficient and extractable by simple measurement procedures. This paper presents the contribution for the establishment of an integrated IC modeling approach whose performance is assessed by direct comparison with the signals measured in laboratory of two distinct memory IC devices. Based on the identification of the main blocks of a typical IC device, the modeling approach consists of a network of system-level sub-models, some of which with already demonstrated accuracy, which simulated the IC interfacing behavior. Emphasis is given to the procedures that were developed to validate by means of laboratory measurements (and not by comparison with circuit-level simulations) the model performance, which is a novel and important aspect that should be considered in the design of IC models that are useful for SI analysis.

/pdf/validation-by-measurements-of-an-ic-modeling-approach-for-5fx8x4dp56.pdf

Validation by Measurements of an IC Modeling Approach for SiP Applications

This paper addresses the generation of behavioral models of digital ICs for signal and power integrity simulations. The proposed models are obtained by external port measurements and by the combined application of specialized state-of-the-art modeling techniques. The proposed approach is demonstrated on the I/O buffers and the core power supply ports of a commercial 90nm flash memory.

/pdf/modeling-of-ic-power-supply-and-i-o-ports-from-measurements-55sm6ym81a.pdf

F. Vitale

Papers

Behavioral Modeling of IC Memories From Measured Data

Modeling of IC power supply and I/O ports from measurements