There can be little doubt that the Monte Carlo method for semiconductor device simulation has enormous power as a research tool. It represents a detailed physical model of the semiconductor material(s), and provides a high degree of insight into the microscopic transport processes. However, if the authority ascribed to Monte Carlo models of devices at 1/spl mu/m feature size is to be maintained for devices below O.1/spl mu/m, modelling of the fundamental physics must be further improved. And if the Monte Carlo method is to be successful as a semiconductor device design tool, the device model must be made more realistic. Success in the industrial sector depends on this, but also on achieving fast run-times optimisation - where the scope and need for ingenuity is now greatest.

The Monte Carlo method for semiconductor device simulation

This paper critically investigates the advantages and limitations of the current-transient methods used for the study of the deep levels in GaN-based high-electron mobility transistors (HEMTs), by evaluating how the procedures adopted for measurement and data analysis can influence the results of the investigation. The article is divided in two parts within Part I. 1) We analyze how the choice of the measurement and analysis parameters (such as the voltage levels used to induce the trapping phenomena and monitor the current transients, the duration of the filling pulses, and the method used for the extrapolation of the time constants of the capture/emission processes) can influence the results of the drain current transient investigation and can provide information on the location of the trap levels responsible for current collapse. 2) We present a database of defects described in more than 60 papers on GaN technology, which can be used to extract information on the nature and origin of the trap levels responsible for current collapse in AlGaN/GaN HEMTs. Within Part II, we investigate how self-heating can modify the results of drain current transient measurements on the basis of combined experimental activity and device simulation.

Deep-Level Characterization in GaN HEMTs-Part I: Advantages and Limitations of Drain Current Transient Measurements

This paper reviews the progress of N-polar () GaN high frequency electronics that aims at addressing the device scaling challenges faced by GaN high electron mobility transistors (HEMTs) for radio-frequency and mixed-signal applications. Device quality (Al, In, Ga)N materials for N-polar heterostructures are developed using molecular beam epitaxy and metalorganic chemical vapor deposition. The principles of polarization engineering for designing N-polar HEMT structures will be outlined. The performance, scaling behavior and challenges of microwave power devices as well as highly-scaled depletion- and enhancement-mode devices employing advanced technologies including self-aligned processes, n+ (In,Ga)N ohmic contact regrowth and high aspect ratio T-gates will be discussed. Recent research results on integrating N-polar GaN with Si for prospective novel applications will also be summarized.

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N-polar GaN epitaxy and high electron mobility transistors

The direct current characteristics of AlGaN/GaN double-channel HEMTs (DC-HEMTs) are investigated by using 2-D numerical simulations. The output characteristics have been predicted with the drift-diffusion, thermodynamic, hydrodynamic, and hot-electron models, respectively. The prediction by the hydrodynamic model is in good agreement with the experiment. It is demonstrated that the hot-electron effect makes a negligible contribution to the negative differential conductance (NDC) of an AlGaN/GaN DC-HEMT; instead, the NDC effect is caused by the self-heating effect. The transfer and transconductance characteristics of an AlGaN/GaN DC-HEMT are also discussed in detail. Finally, a new In0.18Al0.82N /GaN/AlGaN/GaN DC-HEMT structure is proposed for optimizing AlGaN/GaN DC-HEMTs.

The Study of Self-Heating and Hot-Electron Effects for AlGaN/GaN Double-Channel HEMTs

This letter studies the effect of AlGaN back barriers in the dc and RF performance of In0.17Al0.83N/GaN high-electron mobility transistors grown on SiC substrates. When compared to conventional structures without a back barrier, the back barrier effectively prevents the degradation of drain-induced barrier lowering and significantly improves the output resistance in sub-100-nm-gate-length devices. The reduction in short-channel effects helps to increase the frequency performance of AlGaN back-barrier devices. For a 65-nm gate length, the current gain cutoff frequency (fT) of a transistor with an AlGaN back barrier is 210 GHz, which is higher than that of the standard device with the same gate length (fT = 195 GHz).

InAlN/GaN HEMTs With AlGaN Back Barriers

This brief aims to show the effects of threading edge dislocations on the DC and RF performance of GaN high-electron mobility transistor (HEMT) devices. A state-of-the-art high-frequency and high-power HEMT was investigated with our full-band cellular Monte Carlo (CMC) simulator, which includes the full details of the band structure and the phonon spectra. A complete characterization of the device has been performed using experimental data to calibrate the few adjustable parameters of the simulator. Thermal simulations were also carried out with commercial software in order to operate the corrections needed to model thermal effects. The approach of Weimann based on the results of Read, Bonch-Bruevich and Glasko, and Po?do?r was then used to model with our CMC code the dislocation effects on the transport properties of HEMT devices. Our simulations indicate that GaN HEMT performance exhibits a fairly large dependence on the density of thread dislocation defects. Furthermore, we show that a threshold concentration exists, above which a complete degradation of the device operation occurs.

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Effects of Threading Dislocations on AlGaN/GaN High-Electron Mobility Transistors

This letter reports an extensive analysis of the charge capture transients induced by OFF-state bias in double heterostructure AlGaN/GaN MIS- high electron mobility transistor grown on silicon substrate The exposure to OFF-state bias induces a significant increase in the ON-resistance (R
 on
) of the devices Thanks to time-resolved on-the-fly analysis of the trapping kinetics, we demonstrate the following relevant results: 1) R
 on
-increase is temperature- and field-dependent, hence can significantly limit the dynamic performance of the devices at relatively high-voltage and high temperature (100 °C-140 °C) operative conditions; 2) the comparison between OFF-state and back-gating stress indicates that the major contribution to the R
 on
-increase is due to the trapping of electrons in the buffer, and not at the surface; 3) the observed exponential kinetics suggests the involvement of point-defects, featuring thermally activated capture cross section; and 4) trapping-rate is correlated with buffer vertical leakage-current and is almost independent to gate-drain length

Kinetics of Buffer-Related R ON -Increase in GaN-on-Silicon MIS-HEMTs

We report a comparison between state-of-the-art GaN and InGaAs HEMTs in terms of the minimum aspect ratio required to limit short-channel effects. DC and RF simulations were carried out through our full-band cellular Monte Carlo simulator, which includes the full details of the band structure and the phonon spectra. Our results indicate that the minimum aspect ratio for GaN devices is 15 for negligible short-channel effects and 10 for reduced short-channel effects. On the other hand, InGaAs devices perform well for lower aspect ratio values such as 7.5 and 4-5 for negligible and reduced effects, respectively. The origin of this difference between GaN and InGaAs HEMTs is believed to be related to the different dielectric constants of the two materials and the corresponding difference in the electric field distributions related to short-channel effects.

Aspect Ratio Impact on RF and DC Performance of State-of-the-Art Short-Channel GaN and InGaAs HEMTs

A new silicon controlled rectifier low voltage triggered (SCR-LVT), to be adopted as protection structure against electrostatic discharge (ESD) events, has been developed and characterized. A high holding voltage has been obtained thanks to the insertion of two parasitic bipolar transistors, achieved adding a n-buried region to a conventional SCR structure. These two parasitic transistors partially destroy the loop feedback gain of the two main npn and pnp BJTs, resulting in an increase of the sustaining (holding) voltage during the ESD event. A strong dependence of the holding voltage with the ESD pulse width has also been observed, caused by self-heating effects. 2D device simulations (DESSIS Synopsys) have been performed obtaining results that perfectly fit the measurements over a wide temperature range (25 degC-125 degC). Using device simulation results , the factors that influence the holding voltage, in terms of temperature dependence, but also in the behavior of the parasitic BJTs, are explained. A guideline to change the SCR holding voltage, related to the SCR design layout without any change to process parameters, is also proposed.

Development of a new high holding voltage SCR-based ESD protection structure

The most important metrics for the high-frequency and high-power performance of microwave transistors are the cut-off frequency fT, and the Johnson figure of merit FoMJohnson We have simulated a state-of-the-art, high-frequency and high-power GaN HEMT using our full band Cellular Monte Carlo (CMC) simulator, in order to study the RF performance and compare different methods to obtain such metrics The current gain as a function of the frequency, was so obtained both by the Fourier decomposition (FD) method and the analytical formula proposed by Akis A cut-off frequency fT of 150 GHz was found in both the transit time analysis given by the analytical approach, and the transient Fourier analysis, which matches well with the 153 GHz value measured experimentally Furthermore, through some physical considerations, we derived the relation between the FoMJohnson as a function of the breakdown voltage, VBD, and the cut-off frequency, fT  Using this relation and assuming a breakdown voltage of 80V as measured experimentally, a Johnson figure of merit of around 20 × 1012V/s was found for the HEMT device analyzed in this work

https://iopscience.iop.org/article/10.1088/1742-6596/193/1/012040/pdf

Fabio Alessio Marino

Papers

Effects of Threading Dislocations on AlGaN/GaN High-Electron Mobility Transistors

Kinetics of Buffer-Related R ON -Increase in GaN-on-Silicon MIS-HEMTs

Aspect Ratio Impact on RF and DC Performance of State-of-the-Art Short-Channel GaN and InGaAs HEMTs

Development of a new high holding voltage SCR-based ESD protection structure

Figures of merit in high-frequency and high-power GaN HEMTs