A new wideband receiver architecture is proposed that employs two separate passive-mixer-based downconversion paths, which enables noise cancelling, but avoids voltage gain at blocker frequencies. This approach significantly relaxes the trade-off between noise, out-of-band linearity and wideband operation. The resulting prototype in 40 nm is functional from 80 MHz to 2.7 GHz and achieves a 2 dB noise figure, which only degrades to 4.1 dB in the presence of a 0 dBm blocker.

A Blocker-Tolerant, Noise-Cancelling Receiver Suitable for Wideband Wireless Applications

An oscillator topology demonstrating an improved phase noise performance is proposed in this paper. It exploits the time-variant phase noise model with insights into the phase noise conversion mechanisms. The proposed oscillator is based on enforcing a pseudo-square voltage waveform around the LC tank by increasing the third-harmonic of the fundamental oscillation voltage through an additional impedance peak. This auxiliary impedance peak is realized by a transformer with moderately coupled resonating windings. As a result, the effective impulse sensitivity function (ISF) decreases thus reducing the oscillator's effective noise factor such that a significant improvement in the oscillator phase noise and power efficiency are achieved. A comprehensive study of circuit-to-phase-noise conversion mechanisms of different oscillators' structures shows the proposed class-F exhibits the lowest phase noise at the same tank's quality factor and supply voltage. The prototype of the class-F oscillator is implemented in TSMC 65-nm standard CMOS. It exhibits average phase noise of -136 dBc/Hz at 3 MHz offset from the carrier over 5.9-7.6 GHz tuning range with figure-of-merit of 192 dBc/Hz. The oscillator occupies 0.12 mm2 while drawing 12 mA from 1.25 V supply.

/pdf/a-class-f-cmos-oscillator-2yqvgodo2p.pdf

A Class-F CMOS Oscillator

In this work a novel LTE user equipment (UE) power consumption model is presented. It was developed for LTE system level optimization, because it is important to understand how network settings like scheduling of resources and transmit power control affect the UE's battery life. The proposed model is based on a review of the major power consuming parts in an LTE UE radio modem. The model includes functions of UL and DL power and data rate. Measurements on a commercial LTE USB dongle were used to assign realistic power consumption values to each model parameter. Verification measurements on the dongle show that the model results in an average error of 2.6 %. The measurements show that UL transmit power and DL data rate determines the overall power consumption, while UL data rate and DL receive power have smaller impact.

/pdf/lte-ue-power-consumption-model-for-system-level-energy-and-1mjascz9r8.pdf

LTE UE Power Consumption Model: For System Level Energy and Performance Optimization

A 250 MS/s 2x interleaved 11 bit pipelined SAR ADC in 40 nm digital CMOS is presented. Each ADC channel consists of a 6b coarse SAR, a dynamic residue amplifier and a 7b fine SAR with a total of two bits of redundancy. Calibration is leveraged to adjust the uncertain gain of the chosen residue amplifier and various other non-idealities. The ADC achieves a peak SNDR of 62 dB at 10 MS/s, and 56 dB for a Nyquist input at 250 MS/s. The low frequency energy per conversion step ranges from 7 fJ at 10 MS/s to 10 fJ at 250 MS/s.

A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS

In cellular receivers, out-of-band blockers are generally managed by surface-acoustic-wave (SAW) filters between the antenna and the low-noise amplifier (LNA). For Time Division Duplexing (TDD), such as GSM, the SAW can be removed if the receiver can handle very large interferers (e.g. in GSM 0dBm 20 MHz away) [1]. Generally SAW filters also perform differential to single-ended (SE) conversion (balun). Once the SAW is removed an SE transceiver eliminates the external balun, reducing cost and attenuation. For the same sensitivity, a SAW-less SE transceiver can have a noise figure (NF) 2 to 3dB higher than a classical one. An SE LNA could be susceptable to couplings from supply and substrate, which are usually rejected through symmetry. Therefore it should become symmetric as closely as possible to the input pin. A SAW-less differential transceiver [2] can also be appealing if it has an NF close to that of classical transceivers. This is because it can have better sensitivity in TDD (a balun attenuates less than a SAW) and it can be very flexible, being usable for both FDD (where duplexers are differential) and TDD.

SAW-less analog front-end receivers for TDD and FDD

A highly-linear software-defined radio operating from 400 MHz to 6 GHz is presented, with the purpose of removing any dedicated filtering at the antenna. Very high resilience to out-of-band interference is achieved thanks to a 2.5 V linear LNA and mixer-based RF blocker filter. The 2 mm2, 40 nm digital CMOS receiver achieves +10 dBm out-of-band IIP3 and >; +70 dBm calibrated IIP2 at 3 dB NF. It tolerates 0 dBm blockers at 20 MHz offset with acceptable blocker NF.

A 40 nm CMOS 0.4–6 GHz Receiver Resilient to Out-of-Band Blockers

This paper presents the design of a low voltage differential signaling (LVDS) receiver for a 1.3 Gb/s physical layer (PRY) interface. The receiver supports a wide input common mode range of 0.05 V to 2.35 V and a minimum input differential signal of 100 mV as specified by the IEEE LVDS standard. The design is implemented in 0.13 /spl mu/m CMOS technology using both thick (3.3 V) and thin (1.2 V) gate oxide devices and the receiver consumes 11 mW of power. The receiver provides the interface between PHY and media access control (MAC) sub-layers.

Low-power LVDS receiver for 1.3Gbps physical layer (PHY) interface

Rapid growth of wireless market and competitive pressure have pushed the electrical performance of Radio Frequency Integrated Circuits (RFICs) to next level. The performance of RFICs at microwave frequencies depends very much on the package parasitic. Hence, the choice of proper packages depending on application of RFICs is of utmost importance. This paper describes our investigation of the effects of packaging (technology and material) on the performance of RFICs for different application areas.

G. Mandal

Papers

A 40 nm CMOS 0.4–6 GHz Receiver Resilient to Out-of-Band Blockers

Low-power LVDS receiver for 1.3Gbps physical layer (PHY) interface

The Effects of Packaging on RFICs