Journal ArticleDOI
PowerPC 603, a microprocessor for portable computers
TLDR
The PowerPC 603 incorporates a variety of features to reduce power dissipation: dynamic idle-time shutdown of separate execution units, low-power cache design, and power considerations for standard cells, data-path elements, and clocking.Abstract:
The PowerPC 603 incorporates a variety of features to reduce power dissipation: dynamic idle-time shutdown of separate execution units, low-power cache design, and power considerations for standard cells, data-path elements, and clocking. System-level features include three software-programmable static power management modes and a hardware-programmable phase-lock loop. Operating at 80 MHz, the 603 typically dissipates 2.2 W, while achieving an estimated 75 Specint92 and 85 Specfp92. >read more
Citations
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Journal Article
A survey of design techniques for system-level dynamic power management : Special section on low-power electronics and design
TL;DR: Dynamic power management (DPM) is a design methodology for dynamically reconfiguring systems to provide the requested services and performance levels with a minimum number of active components or a minimum load on such components as mentioned in this paper.
Journal ArticleDOI
A survey of design techniques for system-level dynamic power management
TL;DR: This paper describes how systems employ power-manageable components and how the use of dynamic reconfiguration can impact the overall power consumption, and survey recent initiatives in standardizing the hardware/software interface to enable software-controlled power management of hardware components.
Journal ArticleDOI
Policy optimization for dynamic power management
TL;DR: A finite-state, abstract system model for power-managed systems based on Markov decision processes is introduced and the problem of finding policies that optimally tradeoff performance for power can be cast as a stochastic optimization problem and solved exactly and efficiently.
Journal ArticleDOI
System-level power optimization: techniques and tools
Luca Benini,Giovanni De Micheli +1 more
TL;DR: This tutorial presents a cohesive view of power-conscious system-level design, which considers systems as consisting of a hardware platform executing software programs, and considers the major constituents of systems: processors, memories and communication resources.
Journal ArticleDOI
Instruction level power analysis and optimization of software
TL;DR: This paper describes an alternative, measurement based instruction level power analysis approach that provides an accurate and practical way of quantifying the power cost of soft-ware and guides the development of general tools and techniques for low power software.
References
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Journal ArticleDOI
Low-power CMOS digital design
TL;DR: In this paper, techniques for low power operation are presented which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations to reduce power consumption in CMOS digital circuits while maintaining computational throughput.
Journal Article
Low-Power CMOS Digital Design
TL;DR: An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations, and is achieved by trading increased silicon area for reduced power consumption.
Journal ArticleDOI
Trading speed for low power by choice of supply and threshold voltages
Dake Liu,Christer Svensson +1 more
TL;DR: In this article, the tradeoff between speed and power consumption for low power consumption in CMOS VLSI by using the supply voltage and the threshold voltage as variables was investigated.
Journal ArticleDOI
Circuit activity based logic synthesis for low power reliable operations
Kaushik Roy,Sharat Prasad +1 more
TL;DR: A system developed to synthesize both finite state machines and combinational logic for low-power applications, called SYCLOP, is described, which tries to minimize the transition density at the internal nodes of a circuit to minimize power dissipation during normal operation.
Proceedings ArticleDOI
Balancing structured and ad-hoc design for test: testing of the PowerPC 603 microprocessor
TL;DR: The testability and manufacturability features implemented in the PowerPC 603 microprocessor are presented, as well as the issues involved in reconciling a common test plan for two fabrication facilities with differing expectations.