Showing papers by "Haitong Li published in 2014"

A SPICE Model of Resistive Random Access Memory for Large-Scale Memory Array Simulation

Abstract: A SPICE model of oxide-based resistive random access memory (RRAM) for dc and transient behaviors is developed based on the conductive filament evolution model and is implemented in large-scale array simulation. The simulations of one transistor-one resistor RRAM array up to 16 kb with wire resistance (Rwire) and capacitance (Cwire) indicate that: 1) resistance-capacitance delay during RESET and leakage current during SET have significant impact on write operations; 2) with array size enlarging, the power dissipation increases during RESET but decreases during SET; and 3) the increased Rwire and Cwire lead to the degradation of high resistance state and the fluctuation of low resistance state, respectively.

Analysis of the Voltage–Time Dilemma of Metal Oxide-Based RRAM and Solution Exploration of High Speed and Low Voltage AC Switching

Abstract: In this paper, the ac electrical characteristics of metal oxide-based resistive random access memory are investigated based on a developed compact model and the experiment. The voltage-time dilemma phenomenon and the impacts of critical factors on resistive switching speed are addressed. Based on predictions of the model, the small parasitic capacitance, low target high resistance, and large thermal resistance are beneficial to accelerate the resistive switching speed both in SET and RESET processes. The high SET speed and low SET voltage can be achieved by tuning the activation energy of oxygen vacancies. While for the RESET process, the barriers of the release of oxygen ions from electrode and the hopping in resistive switching layer should be turned down simultaneously for high switching speed and low operation voltage.

Write disturb analyses on half-selected cells of cross-point RRAM arrays

Abstract: Write disturb on half-selected (HS) cells is investigated through electrical measurements and large-scale array simulations. The experimental results collected from the individual devices under constant stress voltage and consecutive pulse operation are correlated with the HS cells in large-scale arrays based on a physics-based SPICE compact model. The impact of write/read disturb on the HS cells at different locations of the arrays is analyzed. Design guidelines for the optimized array size based on the experimental data and HSPICE simulations are presented: e.g., a 16 kb array can maintain its stored data pattern for 5×106 pulses and will have 164 false bits among half-selected cells after write disturb.

Towards high-speed, write-disturb tolerant 3D vertical RRAM arrays

Abstract: 3D RRAM array suffers more serious reliability issues than 2D array due to the additional dimension involved. This paper systematically assesses the cell-location-dependent write-access (selected cells) and disturbance issues (unselected cells) for a 3D vertical RRAM array. Using a combination of experiments and simulations, a methodology is developed to enable array-level evaluation by conducting single-device measurements and without the need to fabricate a full 3D array. Based on this evaluation method, it is found that a double-sided bias (DSB) scheme improves write-disturb tolerance by a factor of 1800 and reduces write latency by 19 % under worst-case analyses.

Statistical assessment methodology for the design and optimization of cross-point RRAM arrays

Abstract: A comprehensive assessment methodology for the design and optimization of cross-point resistive random access memory (RRAM) arrays is developed based on a simulation platform implementing an RRAM SPICE model with intrinsic variation effects. A statistical assessment of write/read functionality and circuit reliability is performed via quantifying the impact of array-level variations on RRAM memory circuits. Operation reliability including write failure probability and write disturb effect is quantified, with a strategy of choosing bias schemes and a Vdd design tradeoff presented. Circuit/device co-design guidelines and requirements are further extracted based on the assessment of a series of figure-of-merits such as energy-delay product, disturb immunity, and interconnect scaling effect. Finally, an optimized cross-point array configuration is designed to boost circuit performance. The developed assessment flow will pave the way towards robust circuit/device co-design.

Parameters extraction on HfO X based RRAM

Abstract: In this work, a novel methodology including the extraction strategy and characterization procedure is developed to extract the physical parameters which dominate the switching characteristics of HfOX based RRAM devices. With the extracted parameters, the retention behaviors of HfOX based RRAM devices are simulated by the atom-level simulation tool and compared with the measurement. The agreement between the simulation and measurement verifies the validity of the developed methodology.

Impact of pulse rise time on programming of cross-point RRAM arrays

Abstract: The role of pulse rise time during RRAM programming of cross-point arrays is investigated. The parasitic components in memory arrays is shown to result in distortion and degradation of the applied pulse on the memory cells (compared to the ideal/as-generated pulse), and will potentially cause programming failure. For the first time, the impact of pulse rising edge on the switching voltage is measured. The degradation and distortion of the applied pulse will result in programming failure when the pulse width becomes narrow. Thus, extra attention must be paid for large scale cross-point architecture in high-speed applications.

Simulation of the RRAM based Nonvolatile SRAM cell

Abstract: This work investigates the performance of RRAM based Non-Volatile SRAM (NV-SRAM) cells. The architecture of NV-SRAM includes a 6T SRAM cell and a couple of one transistor-one resistive memory devices configuration. RRAM is controlled by MOSFETs in 1T1R configuration. The performance of NV-SRAM cell is investigated by circuit simulation with a SPICE compact model of oxide-based resistive random access memory based on the conductive filament evolution model.

A comprehensive speed-power analysis of resistive switching memory arrays with selection devices

Abstract: In this work, a comprehensive analysis is performed to study the speed-power performance of one selector-one resistor (1S-1R) and one transistor-one resistor (1T-1R) resistive random access memory (RRAM) arrays, using a physics-based SPICE model of RRAM. It is found that for 1S-1R applications, high turn-on voltage and low conductivity of selectors are beneficial for power reduction, while low turn-on voltage and high conductivity are required for high-speed applications. High nonlinearity of selectors is critical for both low-power and high-speed 1S-1R applications. For 1T-1R arrays, interconnect RC components will impact energy consumption and RC delay, which may set a major limitation to high-speed low-power RRAM applications.

Optimization of uniformity in resistive switching memory by reducing thermal effect

Abstract: In this paper, a technical solution to suppress the fluctuation of resistive switching in resistive random access memory (RRAM) is proposed based on the physical understanding. To investigate the impact of thermal effect, we focus on ion migration affected by diffusion/drift forces and Joule heating. The results reveal that the duration of pulse width results in larger variation in LRS distribution due to oxygen ions diffusion assisted by thermal effect, while it has little impact on HRS distribution. Thus shorter pulse width is preferred to achieve better uniformity. The correctness of the proposed method is verified by the measured data.