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Han Zhao

Researcher at University of Texas at Austin

Publications -  60
Citations -  1132

Han Zhao is an academic researcher from University of Texas at Austin. The author has contributed to research in topics: MOSFET & Gate dielectric. The author has an hindex of 22, co-authored 60 publications receiving 1092 citations.

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InGaAs Tunneling Field-Effect-Transistors With Atomic-Layer-Deposited Gate Oxides

TL;DR: In this paper, the impact of tunneling junction structures on TFETs' performance has been investigated, and it has been found that In0.7Ga0.3As TFET with the p+ (4 nm)/undoped (8 nm) junction provided an on-current of 50 μA/μm and a minimum subthreshold swing (SS) of 86 mV/dec.
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Effects of barrier layers on device performance of high mobility In0.7Ga0.3As metal-oxide-semiconductor field-effect-transistors

TL;DR: In this article, the authors have applied single InP barrier layer with different thicknesses and InP/In0.52Al0.48As double-barrier layer to In0.7Ga0.3As Al2O3 metal-oxide-semiconductor field effect transistors (MOSFETs).
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Self-aligned n-channel metal-oxide-semiconductor field effect transistor on high-indium-content In0.53Ga0.47As and InP using physical vapor deposition HfO2 and silicon interface passivation layer

TL;DR: In this article, the electrical and material characteristics of TaN∕HfO2∕In0.53Ga0.47As and InP substrate metal-oxide-semiconductor capacitors and self-aligned n-channel MOSFETs with physical vapor deposition Si interface passivation layer were presented.
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$\hbox{In}_{0.7}\hbox{Ga}_{0.3}\hbox{As}$ Tunneling Field-Effect Transistors With an $I_{\rm on}$ of 50 $\mu\hbox{A}/\mu\hbox{m}$ and a Subthreshold Swing of 86 mV/dec Using $\hbox{HfO}_{2}$ Gate Oxide

TL;DR: In this paper, tunneling field effect transistors are demonstrated with a high on-current of 50 μA/μm and a minimum sub-threshold swing (SS) of 86 mV/dec using atomic-layer-deposited HfO2 gate oxide.
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High performance In0.7Ga0.3As metal-oxide-semiconductor transistors with mobility >4400 cm2/V s using InP barrier layer

TL;DR: In this paper, the authors investigated device performance for In0.7Ga0.3As with and without InP barrier layer using atomic layer deposited Al2O3 gate dielectric.