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Heiko Falk

Researcher at Hamburg University of Technology

Publications -  72
Citations -  1622

Heiko Falk is an academic researcher from Hamburg University of Technology. The author has contributed to research in topics: Compiler & Cache. The author has an hindex of 20, co-authored 68 publications receiving 1488 citations. Previous affiliations of Heiko Falk include University of Ulm & Technical University of Dortmund.

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Proceedings ArticleDOI

TACLeBench: a benchmark collection to support worst-case execution time research

TL;DR: Open-source programs are collected, adapted to a common coding style, and provided in open-source, with the main features of TACLeBench, which is that all programs are self-contained without any dependencies on standard libraries or an operating system.
Journal ArticleDOI

Building timing predictable embedded systems

TL;DR: The intention of this article is to summarize the current state of the art in research concerning how to build predictable yet performant systems, and suggest precise definitions for the concept of “predictability”, and present predictability concerns at different abstraction levels in embedded system design.
Proceedings ArticleDOI

Optimal static WCET-aware scratchpad allocation of program code

TL;DR: This paper presents an optimal static SPM allocation algorithm that minimizes WCETs by placing the most beneficial parts of a program's code in an SPM and underline the effectiveness of the proposed techniques.
Proceedings ArticleDOI

A Unified WCET Analysis Framework for Multi-core Platforms

TL;DR: This work differs by modeling the interaction of shared cache and shared bus with other basic micro-architectural components (e.g. pipeline and branch predictor) by assuming a timing anomaly free multi-core architecture for computing the WCET.
Journal ArticleDOI

A compiler framework for the reduction of worst-case execution times

TL;DR: Concepts and infrastructures for WCET-aware code generation and optimization techniques forWCET reduction help to obtain code explicitly optimized for its worst-case timing, to automate large parts of the real-time software design flow, and to reduce costs of a real- time system by allowing to use tailored hardware.