Heinrich Meyr

TL;DR: In this paper, a framework for determining power-efficient instruction encoding is presented and the output is an optimized instruction encoding under the constraints of a well-defined cost model that minimizes the power consumption of the instruction bus and the instruction memory.

TL;DR: The verification flow includes the idea of automatic assertion generation during high-level synthesis and support for automatic test-generation utilizing the ADL-framework for ASIP design, and shows the benefit of the approach by trapping errors in a pipelined SPARC-compliant processor architecture.

TL;DR: The 2PARMA project focuses on the definition of a parallel programming model combining component-based and single-instruction multiple-thread approaches, instruction set virtualisation based on portable byte-code, run-time resource management policies and mechanisms as well as design space exploration methodologies for Many-core Computing Fabrics.

TL;DR: A methodology and the necessary tooling for a multiprocessor debugging environment which allows a flexible runtime tradeoff between observability and simulation speed is proposed.

TL;DR: The authors extend RTL code generation from ADL models with the automatic generation of memory interfaces by introducing a new abstract and versatile description format for memory interfaces and their timing protocols.