Probability Distributions.- Linear Models for Regression.- Linear Models for Classification.- Neural Networks.- Kernel Methods.- Sparse Kernel Machines.- Graphical Models.- Mixture Models and EM.- Approximate Inference.- Sampling Methods.- Continuous Latent Variables.- Sequential Data.- Combining Models.

Pattern Recognition and Machine Learning

Fundamentals Of Statistical Signal Processing

Monte Carlo methods are revolutionizing the on-line analysis of data in fields as diverse as financial modeling, target tracking and computer vision. These methods, appearing under the names of bootstrap filters, condensation, optimal Monte Carlo filters, particle filters and survival of the fittest, have made it possible to solve numerically many complex, non-standard problems that were previously intractable. This book presents the first comprehensive treatment of these techniques, including convergence results and applications to tracking, guidance, automated target recognition, aircraft navigation, robot navigation, econometrics, financial modeling, neural networks, optimal control, optimal filtering, communications, reinforcement learning, signal enhancement, model averaging and selection, computer vision, semiconductor design, population biology, dynamic Bayesian networks, and time series analysis. This will be of great value to students, researchers and practitioners, who have some basic knowledge of probability. Arnaud Doucet received the Ph. D. degree from the University of Paris-XI Orsay in 1997. From 1998 to 2000, he conducted research at the Signal Processing Group of Cambridge University, UK. He is currently an assistant professor at the Department of Electrical Engineering of Melbourne University, Australia. His research interests include Bayesian statistics, dynamic models and Monte Carlo methods. Nando de Freitas obtained a Ph.D. degree in information engineering from Cambridge University in 1999. He is presently a research associate with the artificial intelligence group of the University of California at Berkeley. His main research interests are in Bayesian statistics and the application of on-line and batch Monte Carlo methods to machine learning. Neil Gordon obtained a Ph.D. in Statistics from Imperial College, University of London in 1993. He is with the Pattern and Information Processing group at the Defence Evaluation and Research Agency in the United Kingdom. His research interests are in time series, statistical data analysis, and pattern recognition with a particular emphasis on target tracking and missile guidance.

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Sequential Monte Carlo methods in practice

物件導向軟體之架構(Object-Oriented Software Construction)探討

This paper presents an overview of progress in the area of multiple input multiple output (MIMO) space-time coded wireless systems. After some background on the research leading to the discovery of the enormous potential of MIMO wireless links, we highlight the different classes of techniques and algorithms proposed which attempt to realize the various benefits of MIMO including spatial multiplexing and space-time coding schemes. These algorithms are often derived and analyzed under ideal independent fading conditions. We present the state of the art in channel modeling and measurements, leading to a better understanding of actual MIMO gains. Finally, the paper addresses current questions regarding the integration of MIMO links in practical wireless systems and standards.

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From theory to practice: an overview of MIMO space-time coded wireless systems

VP's message

In this paper, we analyze the error rate degradation caused by the finite-precision extrinsic log-likelihood ratio (LLR), i.e., demapper output, for multiple-input multiple-output (MIMO) bit-interleaved coded modulation with iterative decoding (BICM-ID). A closed-form expression for the probability density function (pdf) of the metric difference with finite precision is derived. This pdf is well-approximated by two approaches, namely the pseudo quantization noise (PQN) model and the pdf tail truncation. Moreover, we interpret such performance degradation as an additional signal-to-noise ratio (SNR) loss. As validated by Monte Carlo simulations, this SNR loss can be directly applied at the first iteration, extending our analysis to non-iterative scenario. This work provides a convenient indicator for deciding the LLR precision in real implementations.

BER analysis for MIMO BICM-ID assuming finite precision of extrinsic LLR

Sophisticated C compiler support for network processors (NPUs) is required to improve their usability and consequently, their acceptance in system design. Nonetheless, high-level code compilation always introduces overhead, regarding code size and performance compared to handwritten assembly code. This overhead results partially from high-level function calls that usually introduce memory accesses in order to save and reload register contents. A key feature of many NPU architectures is hardware multithreading support, in the form of separate register files, for fast context switching between different application tasks. In this paper, a new NPU code optimization technique to use such HW contexts is presented that minimizes the overhead for saving and reloading register contents for function calls via the runtime stack. The feasibility and the performance gain of this technique are demonstrated for the Infineon Technologies PP32 NPU architecture and typical network application kernels.

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An Interprocedural Code Optimization Technique for Network Processors Using Hardware Multi-Threading Support

The process of designing an ASIC implementation of a digital receiver is carried out on different levels of abstraction. This often involves the error-prone transition between different description styles which imposes obstacles on the joint optimization of algorithm and architecture.

Efficient VHDL Code Generation for Digital Receiver Design

The move towards higher levels of abstraction in hardware design begins to blur the difference between hardware and software design. Nevertheless, the attractiveness of a software implementation is still defined by the much smaller abstraction gap between specification and implementation. Whereas, hardware design creates the possibility to exploit parallelism at a very fine level of granularity and thereby achieve tremendous performance gains with a moderate expenditure of hardware. This paper describes the joint design process leading to an ASIC chipset accelerating the execution of rulebased systems. The interaction between the algorithm used for software implementation and the parallel algorithm suited for hardware implementation is examined. An area efficient implementation of the programmable hardware was enabled by an application specific compiler backend. The heuristics applied by the optimising “code” generator are discussed quantitatively.

Heinrich Meyr

Papers

VP's message

BER analysis for MIMO BICM-ID assuming finite precision of extrinsic LLR

An Interprocedural Code Optimization Technique for Network Processors Using Hardware Multi-Threading Support

Efficient VHDL Code Generation for Digital Receiver Design

Codesign of a parallel architecture and an optimizing compiler backend: SIN Rete processing as a case study