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Heinrich Meyr

Researcher at RWTH Aachen University

Publications -  326
Citations -  12415

Heinrich Meyr is an academic researcher from RWTH Aachen University. The author has contributed to research in topics: Fading & Instruction set. The author has an hindex of 51, co-authored 326 publications receiving 12170 citations. Previous affiliations of Heinrich Meyr include Synopsys & École Normale Supérieure.

Papers
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Proceedings ArticleDOI

Channel-aware local search (CA-LS) for iterative MIMO detection

TL;DR: By reformulating the detection criterion, the log-likelihood ratio (LLR) computations and searches of the CA-LS are greatly simplified and compared with other practical iterative MIMO detectors, e.g., the list sphere decoder, theCA-LS achieves superior performance in both error rate and complexity aspects.
Proceedings ArticleDOI

Evaluation of Beamforming for Broadcast Applications in Single Frequency Networks

TL;DR: This paper examines the application of beamforming in a single frequency network (SFN), showing significant gains for realistic numbers of transmit antennas at the base stations and numbers of users in the SFN.
Proceedings ArticleDOI

A novel approach to the integration of simulation and implementation to digital signal processing systems

TL;DR: In order to achieve application-specific implementations, the code generator supports tradeoffs between implementation constraints such as code size, throughput, or latency, and a wide spectrum of different optimization strategies has been incorporated in the code generators.
Proceedings ArticleDOI

A universal coprocessor and its application for an ADSL modem

TL;DR: This case study focuses on the design of a universal reusable coprocessor with application specific configurations to accelerate computational intensive tasks for essential parts of an ADSL transceiver.
Journal ArticleDOI

Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors

TL;DR: A high-level specification and design methodology for partially reconfigurable VLIW processors is proposed in this article, resulting in intuitive design decisions and hard-to-retarget processor design tools.