International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

High-performance CMOS variability in the 65-nm regime and beyond. IBM J Res And Dev

An efficient way to reduce the power consumption of electronic devices is to lower the supply voltage, but this voltage is restricted by the thermionic limit of subthreshold swing (SS), 60 millivolts per decade, in field-effect transistors (FETs). We show that a graphene Dirac source (DS) with a much narrower electron density distribution around the Fermi level than that of conventional FETs can lower SS. A DS-FET with a carbon nanotube channel provided an average SS of 40 millivolts per decade over four decades of current at room temperature and high device current I60 of up to 40 microamperes per micrometer at 60 millivolts per decade. When compared with state-of-the-art silicon 14-nanometer node FETs, a similar on-state current Ion is realized but at a much lower supply voltage of 0.5 volts (versus 0.7 volts for silicon) and a much steeper SS below 35 millivolts per decade in the off-state.

https://science.sciencemag.org/content/sci/361/6400/387.full.pdf

Dirac-source field-effect transistors as energy-efficient, high-performance electronic switches

The capacitor is a key element of electronic devices and is characterized by positive capacitance. However, a negative capacitance (NC) behaviour may occur in certain cases and implies a local voltage drop opposed to the overall applied bias. Therefore, a local NC response results in voltage enhancement across the rest of the circuit. Within a suitably designed heterostructure, ferroelectrics display such an NC effect, and various ferroelectric-based microelectronic and nanoelectronic devices have been developed, showing improved performance attributed to NC. However, the exact physical nature of the NC response and direct experimental evidence remain elusive or controversial thus far. In this Review, we discuss the physical mechanisms responsible for ferroelectric NC, tackling static and transient NC responses. We examine ferroelectric responses to voltage and charge, as well as ferroelectric switching, and discuss proof-of-concept experiments and possibilities for device implementation. Finally, we highlight different approaches for the optimization of the intrinsic NC response to maximize voltage amplification. Ferroelectrics-based materials can display a negative capacitance (NC) effect, providing an opportunity to implement NC in electronic circuits to improve their performance. In this Review, the authors discuss static and transient NC responses in ferroelectrics and highlight proof-of-concept experiments and possibilities for device implementation.

/pdf/ferroelectric-negative-capacitance-4jdlwf68kw.pdf

Ferroelectric negative capacitance

A vertical dielectrically modulated tunnel field-effect transistor (V-DMTFET) as a label-free biosensor has been investigated in this paper for the first time and compared with lateral DMTFET (L-DMTFET) using underlap concept and gate work function engineering. To improve the performance of lateral biosensor (LB), a heavily doped front gate ${n}^{+}$ -pocket and gate-to-source overlap is introduced in the vertical biosensor (VB). The integrated effect of lateral tunneling as well as vertical tunneling in VB leads to enhanced ON-state current and decrease the subthreshold swing. To evaluate sensing ability of these devices, charged and charged neutral biomolecules are immobilized in nanogap cavity independently. A deep analysis has been performed to show the effect of variation in dielectric constant ( $k$ ), charge density ( $\rho $ ), ${x}$ -composition of Ge, % volume filling of ${t}_{\textsf {cavity}}$ , length and thickness of a ${n}^{+}$ -pocket and sensitivity of electrical parameters is also incorporated. Dual-pocket (front and back gate pocket) VB is studied and compared with the LB and VB in the tabular form. Noise characteristic of dielectrically modulated field-effect transistor, L-DMTFET, and V-DMTFET is also evaluated.

Performance Assessment of A Novel Vertical Dielectrically Modulated TFET-Based Biosensor

The effect of a triple metal-gate (TMG) on the performance and on the ambipolar current in a TMG vertical tunnel field-effect transistor with triple metal-gate (TMG-TFET) is investigated using technology computer-aided design simulation. The TMG-TFET is designed to tackle the performance as well as the ambipolar current, simultaneously, by modulating the TMG parameters—the work function of the TMG and/or the length of each MG—that have critical impacts on the energy-band diagrams of the channel region. The tempered on-/off-current ratio of $10^{\mathrm { {8}}}$ and the steep average subthreshold slope of 43.5 mV/decade at a power supply voltage of 0.5 V are ascribed to the formation of an energy barrier in the channel by the optimal device parameters. It is found that two main flaws in a conventional (single-material gate) TFET, which are the degraded on-state current and the ambipolar current, can be successfully controlled by adjusting the TMG structure.

Vertical Tunnel FET: Design Optimization With Triple Metal-Gate Layers

The negative capacitance (NC) of ferroelectric materials has paved the way for achieving sub-60-mV/decade switching feature in complementary metal-oxide-semiconductor (CMOS) field-effect transistors, by simply inserting a ferroelectric thin layer in the gate stack. However, in order to utilize the ferroelectric capacitor (as a breakthrough technique to overcome the Boltzmann limit of the device using thermionic emission process), the thickness of the ferroelectric layer should be scaled down to sub-10-nm for ease of integration with conventional CMOS logic devices. In this paper, we demonstrate an NC fin-shaped field-effect transistor (FinFET) with a 6-nm-thick HfZrO ferroelectric capacitor. The performance parameters of NC FinFET such as on-/off-state currents and subthreshold slope are compared with those of the conventional FinFET. Furthermore, a repetitive and reliable steep switching feature of the NC FinFET at various drain voltages is demonstrated.

Sub-60-mV/decade Negative Capacitance FinFET With Sub-10-nm Hafnium-Based Ferroelectric Capacitor

An optimally designed germanium-source vertical tunnel FET (V-TFET) is investigated using technology computer aided design simulation. Three consecutive band-to-band tunneling (BTBT) mechanisms (i.e., lateral, vertical, and additional vertical BTBT) are used in the V-TFET to enhance its performance as well as to maintain an average subthreshold slope below 60 mV/decade at 300 K. The impact of various V-TFET parameters on its performance is also investigated. Furthermore, the impact of threshold voltage variation ( $\sigma V_{\textrm {TH}}$ ) due to random variability [e.g., line-edge roughness (LER) and random dopant fluctuation (RDF)] on the performance of the V-TFET is studied. The LER in the V-TFET is found that the electric field is increased by the LER in the source region, resulting in the generation of lucky paths, which can lead to increase $\sigma V_{\textrm {TH}}$ . Without a gate-to-source overlap region in the V-TFET, RDF/LER-induced $\sigma V_{\textrm {TH}}$ is considerably increased by a lateral tunneling mechanism. As a result, the gate-to-source overlap region in the V-TFET is critical to enhancing the performance and designing a variation-aware V-TFET. Last but not least, field-induced quantum confinement leads to delay the onset voltage of the vertical BTBT, so that the device performance and process-induced random variation (especially, RDF) are significantly deteriorated.

Study of Random Variation in Germanium-Source Vertical Tunnel FET

In this letter, a semi-analytical current–voltage model for a negative capacitance field-effect transistor (NCFET) with a ferroelectric material ( i.e. , BaTiO3) is proposed. Surface potential ( $\psi _{\mathrm {S}})$ in the channel region is determined first by solving the Landau–Khalatnikov (LK) equation numerically with Poisson’s equation. Then, the drain–current is achieved based on the current continuity equation using $\psi _{\mathrm {S}}$ determined earlier. In addition, by introducing a fitting potential for a given drain–voltage, threshold voltage shift can be captured, resulting in accurate surface potential and drain–current at different gate voltages. We have verified our model using the technology computer-aided design (TCAD)-MATLAB simulation, and our model exhibits an excellent agreement to the simulation results. In addition, the impacts of the ferroelectric thickness and channel doping concentration on the device performance and hysteresis window of NCFET are thoroughly explored.

Current-Voltage Model for Negative Capacitance Field-Effect Transistors

A variation-immune symmetric tunnel field-effect transistor (S-TFET) is proposed for the first time to implement bidirectional current flows ( $I_{\mathrm{{\scriptstyle ON}}}=3.6~\mu $ A/ $\mu $ m, $I_{\mathrm{{\scriptstyle OFF}}}=23$ pA/ $\mu $ m at $V_{\mathrm {DD}}= 0.5$ V) with the steep-switching feature of a subthreshold slope (SS) $ mV/dec ( ${\rm SS} = 47$ mV/dec) and to alleviate the impact of random variation. A random variation analysis with the three major random variation sources, i.e., line-edge roughness, random dopant fluctuation, and work-function variation, is performed to quantitatively evaluate the impact of each variation source on the performance of the device. To perform variation-aware design for the S-TFET, the key device parameter (i.e., the thickness of the intrinsically doped silicon pad layer) is optimized to minimize the impact of random variation on the threshold voltage ( $V_{T}$ ) and SS. For ultralow power applications with a sub-0.5 V power supply voltage ( $V_{{\rm {DD}}}$ ), the variation-robust S-TFET is one of several promising device structures.

Hyunjae Lee

Papers

Vertical Tunnel FET: Design Optimization With Triple Metal-Gate Layers

Sub-60-mV/decade Negative Capacitance FinFET With Sub-10-nm Hafnium-Based Ferroelectric Capacitor

Study of Random Variation in Germanium-Source Vertical Tunnel FET

Current-Voltage Model for Negative Capacitance Field-Effect Transistors

Random Variation Analysis and Variation-Aware Design of Symmetric Tunnel Field-Effect Transistor