Showing papers in "IEEE Journal of the Electron Devices Society in 2017"
TL;DR: The 2-D physics based TCAD numerical simulation analysis of the AlGaN/GaN high-electron mobility transistors suggests that LF admittance dispersion is an effective tool in identifying the traps present in the GaN buffer.
Abstract: In this paper, the type, activation energy ( $\textit{E}_{a}$ ) and cross section ( ${\sigma }_{n}$ ) of the GaN buffer traps existing in the AlGaN/GaN high-electron mobility transistors are investigated through low frequency (LF) S-parameters measurements. Furthermore, we present the 2-D physics based TCAD numerical simulation analysis of this device. The dc simulation results are calibrated to match with the experimentally measured I–V characteristics and this allows to qualitatively estimate the concentration of traps ( $\textit{N}_{T}$ ) present in the GaN buffer. Knowing the measured trap energy level and the estimated trap concentration $\textit{N}_{T}$ , TCAD physical simulations are performed at various temperatures in order to extract the LF- $\textit{Y}_{22}$ admittance parameter. Interestingly, the LF- $\textit{Y}_{22}$ simulation results are found to be in good agreement with the measurements and this result strongly suggests that LF admittance dispersion is an effective tool in identifying the traps present in the GaN buffer. Moreover, this paper reveals that acceptor-like traps with an apparent concentration of $5.0\times 10^{16}$ cm $^{-3}$ and with the apparent trap energy level of 0.4 eV below the conduction band are located in the GaN buffer.
74 citations
TL;DR: In this article, 3D printing is used to fabricate mold for micro-structuring the polydimethylsiloxane (PDMS) elastomeric dielectric layer in capacitive flexible pressure sensors.
Abstract: 3-D printing is used to fabricate mold for micro-structuring the polydimethylsiloxane (PDMS) elastomeric dielectric layer in capacitive flexible pressure sensors. It is shown that, despite of the limited resolution of the used commercial 3-D printer for producing the mold, the fabricated sensor with the micro-structured PDMS layers can achieve sensitivity higher than previous work using micro-fabricated silicon wafer molds. The devices also present very low detection limit, fast response/recovery speed, excellent durability and good tolerance to variations of ambient temperature and humidity, which enables to reliably monitor weak human physiological signals in real time. As an application example, the flexible pressure sensor is integrated in a wearable system to monitor wrist pulse.
67 citations
TL;DR: In this article, a method to improve thermal management of Ga2O3 FETs is demonstrated via simulation of epitaxial growth on a 4H-SiC substrate using a recently published device as a model.
Abstract: A method to improve thermal management of ${\beta }$ -Ga2O3 FETs is demonstrated here via simulation of epitaxial growth on a 4H-SiC substrate Using a recently published device as a model, the reduction achieved in self-heating allows the device to be driven at higher gate voltages and increases the overall performance For the same operating parameters an 18% increase in peak drain current and 15% reduction in lattice temperature are observed Device dimensions may be substantially reduced without detriment to performance and normally off operation may be achieved
55 citations
TL;DR: In this paper, the negative capacitance (NC) of ferroelectric materials has paved the way for achieving sub-60mV/decade switching feature in complementary metal-oxide-semiconductor (CMOS) field effect transistors.
Abstract: The negative capacitance (NC) of ferroelectric materials has paved the way for achieving sub-60-mV/decade switching feature in complementary metal-oxide-semiconductor (CMOS) field-effect transistors, by simply inserting a ferroelectric thin layer in the gate stack. However, in order to utilize the ferroelectric capacitor (as a breakthrough technique to overcome the Boltzmann limit of the device using thermionic emission process), the thickness of the ferroelectric layer should be scaled down to sub-10-nm for ease of integration with conventional CMOS logic devices. In this paper, we demonstrate an NC fin-shaped field-effect transistor (FinFET) with a 6-nm-thick HfZrO ferroelectric capacitor. The performance parameters of NC FinFET such as on-/off-state currents and subthreshold slope are compared with those of the conventional FinFET. Furthermore, a repetitive and reliable steep switching feature of the NC FinFET at various drain voltages is demonstrated.
53 citations
TL;DR: Predicted comparable performances and densities, with considerations of the complexity/cost of GAAFET processing versus that of the FinFET with pragmatic simplifications, suggest that theFinFET is the better choice for the future.
Abstract: Speed and power performances of Si-based stacked-nanowire gate-all-around (GAA) FETs and pragmatic ultra-thin-fin FETs at the 5nm CMOS technology node are projected, compared, and physically explained based on 3-D numerical simulations. The respective device domains are also used to compare integration densities based on 6T-SRAM layouts. Predicted comparable performances and densities, with considerations of the complexity/cost of GAAFET processing versus that of the FinFET with pragmatic simplifications, suggest that the FinFET is the better choice for the future.
47 citations
TL;DR: In this article, a consistent DC to RF modeling solution for Al gallium nitride (GaN)/GaN high electron mobility transistors is demonstrated that is constructed around a surfacepotential-based core.
Abstract: In this paper, a consistent DC to RF modeling solution for Al gallium nitride (GaN)/GaN high electron mobility transistors is demonstrated that is constructed around a surface-potential-based core. Expressions for drain current and intrinsic terminal charges in the form of surface-potential are used to simultaneously model the DC characteristics and the intrinsic capacitances of a commercial GaN device. Self-heating and trapping effects are incorporated to account for the non-linear nature of the device. We discuss the parameter extraction flow for some of the key model parameters that are instrumental in fitting the DC characteristics, which simultaneously determines the bias-dependent intrinsic capacitances and conductances that significantly eases the RF parameter extraction. Parasitic capacitances, gate finger resistance, and extrinsic bus-inductances are extracted, from a single set of measured non-cold-FET S-parameters, using the model process design kit. The extraction procedure is validated through overlays of broadband (0.5–50 GHz) S-parameters, load-pull and harmonic-balance (10 GHz) simulations against measured data, under multiple bias conditions to successfully demonstrate the model performance at large-signal RF excitations.
44 citations
TL;DR: In this article, an enhancement-mode high-electron-mobility transistor with a p-GaN gate was fabricated by using a chemistry-ease Cl2/N2/O2-based inductively coupled plasma etching technique.
Abstract: An enhancement-mode high-electron-mobility transistor with a p-GaN gate was fabricated by using a chemistry-ease Cl2/N2/O2-based inductively coupled plasma etching technique. This etching technique features a precise etching self-termination at the AlGaN barrier surface, which enables a broad process window with a large tolerance of etching time. With a post-annealing process, the property of two-dimensional electron gas (2DEG) can be restored to a high level after the etching. The mechanisms of etching self-termination and 2DEG recovery were clarified. The fabricated device exhibits a drain saturation current of 355 mA/mm with a threshold voltage of +1.1 V, an on/off ratio of $10^{7}$ , and a static on-resistance ${R} _{\mathrm{ ON}}$ of $10~{\Omega }\cdot $ mm. Furthermore, normally-off operation of the device can be achieved across the wafer.
43 citations
TL;DR: In this paper, a ferroelectric thin film transistor (Fe-TFT) based on annealing-free hafnium zirconium oxide (HfZrO) is demonstrated.
Abstract: A ferroelectric thin film transistor (Fe-TFT) based on annealing-free hafnium zirconium oxide (HfZrO) is demonstrated in this paper. Indium zinc oxide was used as channel semiconductor. The as-deposited 30-nm HfZrO film implemented as gate dielectric was proved to be crystallized with a mixture of monoclinic, tetragonal, and orthorhombic phases and showed ferroelectricity naturally. Thus, high temperature annealing process was avoided. The transfer characteristic of this Fe-TFT was demonstrated with operating voltage that was smaller than 3 V, memory window about 1 V, and small subthreshold slope (SS) about 82 mV/dec. The charge trapping phenomenon in this device was explored by characterizing the transfer curves with different ranges of gate voltages. This HfZrO-based device with low processing thermal budget and small SS has high potential for Fe-TFT memory which can be used in oxide semiconductor-based systems and applications.
39 citations
TL;DR: In this paper, the design and fabrication of fine-pitch and pixelated-addressed micro-light emitting diode (LED) arrays with emission wavelengths of red (R), green (G), blue (B), and infrared (IR) were reported.
Abstract: In this paper, we report the design and fabrication of fine-pitch and pixelated-addressed micro-light emitting diode (LED) arrays with emission wavelengths of red (R), green (G), blue (B), and infrared (IR). The arrays have a resolution of $8\times 8$ with monochromatic LED chips directly bonded to custom-designed printed circuit boards to form pixelated matrix. R, G, B, and IR micro-LED arrays with a pixel pitch of 1 mm were demonstrated. Sequential row scanning and multiple columns programming is performed by two CMOS-based application specific integrated circuit chips providing constant-sinking current and forward voltage for each pixel of the micro-LED arrays. The uniformity of operating current and forward voltage of the micro-LED pixels was measured with 1.94% coefficient of variation. The micro-LED pixel has much shorter rising time and higher response frequency than those of regular packaged blue and white LEDs. The implemented R–G–B micro-LED arrays are the excellent candidate for high-definition fine-pitch LED displays and demonstrated its versatile functionalities such as visible light communications. The IR micro-LED arrays show great potential in health medical treatment, IR detection imaging and local positioning system.
39 citations
TL;DR: A voltage programmed pixel circuit based on amorphous-indium-gallium-zincoxide thin-film transistors (a-IGZO TFTs) for active-matrix organic light-emitting displays was proposed in this article.
Abstract: In this paper, we propose a novel voltage programmed pixel circuit based on amorphous-indium-gallium-zinc-oxide thin-film transistors (a-IGZO TFTs) for active-matrix organic light-emitting displays. Through the extensive simulation work based on a-IGZO TFT and OLED models, we confirm that the proposed pixel circuit can compensate for threshold voltage variations of TFTs and OLED degradation over wide dynamic range (~104) of OLED current as well as achieve a high pixel aperture ratio with the suppressed OLED current error rate below 9%.
32 citations
TL;DR: In this article, the authors have designed and fabricated GaN static induction transistor using self-aligned technology, which was accomplished mainly by using a SiO2 lift-off step in buffered oxide etch (BOE).
Abstract: The rapid development of RF power electronics requires amplifier operating at high frequency with high output power. GaN-based HEMTs as RF devices have made continuous progress in the last two decades showing great potential for working up to G band range. However, vertical structure is preferred to obtain higher output power. In this paper, we have designed and fabricated GaN static induction transistor using the self-aligned technology, which was accomplished mainly by using a SiO2 lift-off step in buffered oxide etch (BOE). By optimizing the time in ultrasonic bath and in BOE, the SiO2 and the metal on top were removed completely which resulted in the gate metal only on the sidewalls. Both dry and wet etch techniques were investigated to reduce the gate leakage on the etched surface. The low power dry etch combined with the tetramethylammonium hydroxide wet etch can effectively reduce the etch damages, decrease the gate leakage and enhance the gate control over the channel.
TL;DR: In this paper, a tunnel FET (TFET)-based power management circuit (PMC) is proposed for ultra-low power RF energy harvesting applications. But the proposed converter is limited to −20 dBm (915 MHz).
Abstract: This paper proposes a Tunnel FET (TFET)-based power management circuit (PMC) for ultra-low power RF energy harvesting applications. In contrast with conventional thermionic devices, the band-to-band tunneling mechanism of TFETs allows a better switching performance at sub-0.2 V operation. As a result, improved efficiencies in RF-powered circuits are achieved, thanks to increased rectification performance at low power levels and to the reduced energy required for a proper PMC operation. It is shown by simulations that heterojunction TFET devices designed with III–V materials can improve the rectification process at received power levels below −20 dBm (915 MHz) when compared to the application of homojunction III–V TFETs and Si FinFETs. For an available power of −25 dBm, the proposed converter is able to deliver 1.1 ${\mu }\text{W}$ of average power (with 0.5 V) to the output load with a boost efficiency of 86%.
TL;DR: In this article, the authors employ a circular thin-film transistor (TFT) structure to improve the stability of amorphous-indium-gallium-zincoxide TFTs under tensile bending strain.
Abstract: We employ a circular (Corbino) thin-film transistor (TFT) structure, in which the outer-ring is the drain and the inner-ring is the source, to improve the stability of amorphous–indium–gallium–zinc–oxide TFTs under tensile bending strain. We attribute the stability improvement to a more uniform electric field distribution across the circular channel, as it is isolated from local electric field crowding at sharp corners or channel edges. In addition, the effect of strain-induced increase in channel charge concentration is small in Corbino TFTs, owing to the larger outer-ring electrode, which depletes more electrons than the drain of rectangular TFTs. Furthermore, the circular shape results in bending direction independence, which is very important in multi-TFT circuits, where TFT orientation varies with position.
TL;DR: In this article, the transient response of negative capacitance (NC) in an organic ferroelectric capacitor is experimentally investigated, where the external series resistor is altered as a tuning parameter to explore the impact of the RC time constant on the NC time duration.
Abstract: The transient response of negative capacitance (NC) in an organic ferroelectric capacitor is experimentally investigated. To observe the transient response of the NC, a simple series network, consisting of an external series resistor and an organic ferroelectric capacitor, is built. The Landau coefficients of the organic ferroelectric capacitor were extracted from the measured polarization versus applied electric field data. A circuit level simulation was provided with the extracted parameters based on the Landau–Khalatnikov equation. To explore the impact of the RC time constant on the NC time duration in the RC series circuit, the external series resistor is altered as a tuning parameter. Also, the effect of various temperatures of the ferroelectric capacitor on the NC time duration is experimented. This paper demonstrates that either the external resistor or the ambient temperature can change the NC time duration in an organic ferroelectric capacitor.
TL;DR: The ZnGaO epilayers were grown on a c-plane sapphire substrate by metalorganic chemical vapor deposition and fabricated into metaloxide-semiconductor field effect transistors (MOSFETs) as discussed by the authors.
Abstract: Zinc gallate (ZnGaO) epilayers were grown on a c-plane sapphire substrate by metalorganic chemical vapor deposition and fabricated into metal-oxide-semiconductor field-effect transistors (MOSFETs). The ZnGaO MOSFETs exhibited a complete channel pinch-off of the drain current for $V_{\mathrm{ GS}} V, high off-state breakdown voltage of 378 V, high $I_{\mathrm{ ON}} /I_{\mathrm{ OFF}} $ ratio of $10^{6}$ , and low gate leakage current.
TL;DR: In this paper, a pixelated two-layer Geiger-mode avalanche sensor designed for the direct detection of charged particles is presented, where each pixel is formed by two vertically aligned avalanche detectors, exploiting the coincidence between two simultaneous avalanche events to discriminate between the detection of particles and dark counts.
Abstract: This paper presents the first experimental demonstration of a pixelated two-layer Geiger-mode avalanche sensor designed for the direct detection of charged particles. In the proposed device, each pixel is formed by two vertically aligned avalanche detectors, exploiting the coincidence between two simultaneous avalanche events to discriminate between the detection of particles and dark counts. A 48 $\times $ 16 pixel array has been designed and fabricated in a 150-nm CMOS process and vertically integrated through bump bonding. The pixel, that includes passive quenching, comparator, and digital electronic circuits for coincidence processing and signal storage, has a size of 50 $\mu \text{m} \,\, \times $ 75 $\mu \text{m}$ and a maximum fill factor of 51.6%. The operation of the particle sensor has been validated with the measurement of dark count rate distribution at different coincidence resolution times. An average dark count rate per pixel as low as 93 mHz, corresponding to 24 Hz/mm2, was obtained at room temperature. A first sensor validation using a 90Sr $\beta $ source is presented.
TL;DR: In this article, a simulation study of vertically stacked lateral nanowires transistors (NWTs), which may have applications at 5-nm CMOS technology, is presented, based on a collection of simulation techniques to capture the complexity in ultra-scaled devices.
Abstract: In this paper, we present a simulation study of vertically stacked lateral nanowires transistors (NWTs), which may have applications at 5-nm CMOS technology. Our simulation approach is based on a collection of simulation techniques to capture the complexity in such ultra-scaled devices. Initially, we used drift-diffusion methodology with activated Poisson–Schrodinger quantum corrections to accurately capture the quantum confinement in the cross-section of the device. Ensemble Monte Carlo simulations are used to accurately evaluate the drive current capturing the complexity of the carrier transport in the NWTs. We compared the current flow in single, double, and triple vertically stacked lateral NWTs with and without contact resistance. The results presented here suggest a consistent link between channel strain and device performance. Furthermore, we propose a device structure for the 5-nm CMOS technology node that meets the required industry scaling projection. We also consider the interplay between various sources of statistical variability and reliability in this paper.
TL;DR: In this paper, high temperature characteristics of bipolar-mode operation of normally off diamond junction field effect transistors were investigated up to 573 K and the experimental current gain decreased with the rise in the gate current.
Abstract: High temperature characteristics of bipolar-mode operation of normally-off diamond junction field-effect transistors were investigated up to 573 K. As an important factor, the current gain depending on the gate current was analyzed with a theoretical model. We found that the experimental current gain decreased with the rise in the gate current, in agreement with the theoretical estimation considering the recombination at the end regions. We achieved 4–9 times higher drain currents in the bipolar-mode compared with the unipolar-mode operation at a DC current gain of 10. Furthermore, the bipolar-mode currents at the high temperatures of 473 and 573 K became two orders of magnitude larger than the unipolar-mode current at room temperature with a large DC current gain of $10^{2}$ .
TL;DR: In this paper, the surface states between the ohmic and Schottky contacts play a more important role than the metal/AlN interface in determining the reverse breakdown and leakage current of AlN Schittky diodes.
Abstract: AlN Schottky diodes with various device geometries were fabricated on sapphire substrate and their temperature-dependent current–voltage characteristics were analyzed. At forward bias, high ideality factors were obtained, indicating a large deviation from the ideal thermionic emission model. At reverse bias, the breakdown voltage showed a negative temperature dependence, and the leakage current was well described using a 2-D variable-range hopping conduction model. Furthermore, the breakdown voltages and leakage currents of the devices showed a strong dependence on the surface distance between the ohmic and Schottky contacts, but a relatively small dependence on the area of the Schottky contacts. These results suggest surface states between ohmic and Schottky contacts play a more important role than the metal/AlN interface in determining the reverse breakdown and leakage current of AlN Schottky diodes. A quantitative study of AlN Schottky diodes at high temperature reveals a geometry-dependent surface breakdown electric field and surface leakage current. Surface passivation and treatments may enhance the device performances and impact the reverse breakdown and current leakage mechanisms. These results will serve as the guidance for the design and fabrication of future AlN electronic devices.
TL;DR: The set operation of HfO2 based 1T-1R arrays is studied by applying incremental step pulse with verify algorithm and the extracted leakage values after the set operation were discussed in the framework of the quantum point contact model.
Abstract: In this paper, the set operation of HfO2 based 1T-1R arrays is studied by applying incremental step pulse with verify algorithm. To evaluate the impact of the voltage step increment on the conduction mechanism of filaments, the voltage increments between consecutive pulses are varied between 0.05 and 0.4 V. The extracted leakage values after the set operation were discussed in the framework of the quantum point contact model. In the so called low resistive state, the conductive filaments demonstrate a defined signature of conductance quantization.
TL;DR: In this paper, the effects of incorporating Fe3O4 into the TiO2 photoelectrode of dye-sensitized solar cell (DSSC) were investigated in detail by atomic force microscope, solar simulator, X-ray diffraction, UV-visible spectroscopy, and electrochemical impedance spectrograph.
Abstract: In this paper, Fe3O4–titanium dioxide (TiO2) composited photoelectrode was prepared by spin coating method. The effects of incorporating Fe3O4 into the TiO2 photoelectrode of dye-sensitized solar cell (DSSC) were investigated in detail by atomic force microscope, solar simulator, X-ray diffraction, UV–visible spectroscopy, and electrochemical impedance spectroscopy. Compared with the photovoltaic conversion efficiency of 2.35% of DSSC based on TiO2 pure photoelectrode, the photovoltaic conversion efficiency of 3.54% was obtained. The experimental results show that the Fe3O4 acted as a catalyst to provide another electron pathway for DSSC, which could lower the condition of electron recombination. Moreover, it could be found from Nyquist plot that the resistance at the interface between electrolyte and TiO2 film increased for DSSC after incorporating Fe3O4 into the TiO2 photoelectrode, which indicated that the condition of electron recombination was restrained.
TSMC1
TL;DR: In this paper, a method for on-chip random telegraph noise (RTN) characteristic time constant extraction using the double sampling circuit in an 8.3 Mpixel CMOS image sensor is described.
Abstract: A new method for on-chip random telegraph noise (RTN) characteristic time constant extraction using the double sampling circuit in an 8.3 Mpixel CMOS image sensor is described. The dependence of the measured RTN on the time difference between the double sampling and the key equation used for time constant extraction are derived from the continuous time RTN model and the discrete event RTN model. Both approaches lead to the same result and describe the data reasonably well. From the detailed study of the noisiest 1000 pixels, we find that about 75% to 85% of them show the signature of a single-trap RTN behavior with three distinct signal levels, and about 96% of the characteristic time constants fall between 1 ${\mathrm{ \mu }}\text{s}$ and 500 ${\mathrm{ \mu }}\text{s}$ with the median around 10 ${\mathrm{ \mu }}\text{s}$ at room temperature.
TL;DR: In this article, a resonator-based MEMS architecture for multi-sensor SOC applications is proposed, where multiple MEMS sensors including environmental temperature sensor, ambient pressure sensor, accelerometer as well as gyro sensor can be monolithically implemented with the readout circuits without off-fab pre/post processes.
Abstract: In this paper, we demonstrated a resonator-based MEMS architecture for multi-sensor SOC applications. A newly developed 0.18 ${\mu }\text{m}$ 1P6M CMOS ASIC/MEMS process was adopted to integrate MEMS sensor and circuits monolithically. By using resonators as the building blocks, multiple MEMS sensors including environmental temperature sensor, ambient pressure sensor, accelerometer as well as gyro sensor can be monolithically implemented with the readout circuits by the single standard ASIC/MEMS process without off-fab pre/post processes. The proposed architecture enables compact and innovative sentient-assisted SOC design for the emerging IOT applications.
TL;DR: In this paper, the authors demonstrated memory and energy storage dual operation in GeS2/Ag conducting bridge RAM, where the same device can be used for data or energy storage, depending on specific bias and current conditions, and the total stored charge was quantified.
Abstract: In this paper, we demonstrated memory and energy storage dual operation in GeS2/Ag conducting bridge RAM. Both operations are based on electrochemical reactions and Ag diffusion in the GeS2 electrolyte. Depending on specific bias and current conditions, the same device can be used for data or energy storage: in memory mode, Ag-based filament is formed in GeS2, while in energy storage mode, Ag bulk diffusion is achieved. Voltage sweep and constant current stress cycling modes for energy storage are evaluated, and the total stored charge is quantified. These obtained results open the path for new autonomous or ultra-low power circuits, integrating dual operation devices composed of the same stack, where energy storage devices could provide energy to the memory array.
TL;DR: In this paper, a thin film transistors (TFTs) with amorphous InMgO (a-IMO) and InGaZnO(a-IGZO) stacked active layers are proposed to implement high-performance ultraviolet (UV) detectors.
Abstract: Thin film transistors (TFTs) with amorphous InMgO (a-IMO) and InGaZnO (a-IGZO) stacked active layers are proposed to implement high-performance ultraviolet (UV) detectors. In this structure, the IGZO layer serves as the conductive layer and the IMO layer acts as the light absorption layer. The fabricated a-IGZO/a-IMO TFT shows comparable electrical characteristics to those of the conventional a-IGZO TFT as well as high UV photocurrent gain with good visible-blindness. In addition, the a-IGZO/a-IMO TFT-based sensor operates with stable and successive light detection. Thus, the a-IGZO/a-IMO TFT has been demonstrated to be able to act as both sensing and switching devices in the pixels of UV image sensors.
TL;DR: In this article, a high-density positive fixed charge (PF) passivation using SiON for GaN MIS-HEMTs was demonstrated on GaN HEMTs, where the positive fixed charges at the interface between passivation and AlGaN surface can reduce the surface potential and expand the quantum well under Fermi level.
Abstract: An effective passivation with high-density positive fixed charges was demonstrated on GaN MIS-HEMTs. The positive fixed charges at the interface between passivation and AlGaN surface can reduce the surface potential and expand the quantum well under Fermi level. Besides, to satisfy charge balance, the net charge density at the AlGaN surface must equal to the 2DEG carrier density. Thus, the positive fixed charges passivation can increase the 2DEG carrier density and improve the switching performance of GaN MIS-HEMTs. In this paper, we demonstrated a high-density positive fixed charges $(\sim 2.71 \times 10^{13} e/cm^{-2})$ passivation using SiON for GaN MIS-HEMTs. The device with SiON passivation exhibits significant improvements in $I$ – $V$ characteristics and dynamic RON compared to the conventional SiN passivated device.
TL;DR: In this article, flexible In2O3 nanowire transistors gated by microporous SiO2-based solid electrolytes are fabricated on paper substrates at room temperature.
Abstract: Flexible In2O3 nanowire transistors gated by microporous SiO2-based solid electrolytes are fabricated on paper substrates at room temperature. Low-voltage (1.0 V) operation of these devices is realized owing to the large electric-double-layer capacitance of (1.73 ${\mu }\text{F}$ /cm2 at 20 Hz) of the microporous SiO2 solid electrolytes, which were deposited at room temperature. The subthreshold swing, current on/off ratio, and field-effect mobility of the paper-based nanowire transistors are estimated to be 74 mV/decade, $1.7\times 10^{6}$ , and 218.3 cm2/ $\text{V}\cdot \text{s}$ , respectively. These low-voltage paper-based nanowire transistors show promise for use in portable flexible paper electronics and low-cost portable sensors.
TL;DR: In this article, the authors demonstrate a new type of silicon-based capacitorless one-transistor dynamic random access memory (1T-DRAM) with an electron-bridge channel.
Abstract: We experimentally demonstrate a new type of silicon-based capacitorless one-transistor dynamic random access memory (1T-DRAM) with an electron-bridge channel. The fabrication steps are fully compatible with modern CMOS technology. An underlap device structure is exploited and positive charges are primarily stored in drain-side and source-side p-type pseudo-neutral regions under the oxide spacer. These regions are isolated by the gate/drain or gate/source depletion regions during programming and read “1” operations which facilitates the device to achieve a 4-second-long retention time at room temperature. The carrier mobility of the electron-bridge 1T-DRAM also exhibits reduced dependence on temperature, thereby the programming window remains viable at high temperatures, while also maintaining 26% of the retention performance at 358 K. The benefits of the planar cell enable the realization of a scalable vertical channel structure.
TL;DR: In this paper, the potential of quinacridone derivatives as organic semiconductors in organic field effect transistors (OFETs) and circuits was investigated using a Suzuki coupling reaction.
Abstract: Poly[quinacridone-alt-quaterthiophene] (PQCQT) was synthesized, using a Suzuki coupling reaction, to investigate the potential of quinacridone derivatives as organic semiconductors in organic fieldeffect transistors (OFETs) and circuits. A PQCQT film annealed at 150 °C yielded quite high field-effect performances, including a hole mobility of $2.0 \times 10^{-2}$ cm2/(Vs). In addition, to confirm the feasibility of using PQCQT in high-voltage circuit applications, electrical behaviors of PQCQT-based OFETs were described by extracting the model parameters of the industry standard compact Berkeley short-channel IGFET model. From the developed OFET model parameter set, we successfully evaluated the circuit operation of a p-type organic inverter with a frequency of 45.5 kHz in an 80 V supply condition.
TL;DR: In this article, the reliability-tolerant design for ultra-thin-body (UTB) GeOI 6T SRAM cell and sense amplifiers was investigated.
Abstract: This paper investigates the reliability-tolerant design for ultra-thin-body (UTB) GeOI 6T SRAM cell and sense amplifiers. For UTB GeOI 6T SRAM cells, using high threshold voltage design significantly mitigates the read and hold static noise margin degradations due to NBTI and PBTI. Due to worse PBTI degradations, as stress (aging) time increases, GeOI current and voltage latch sense amplifiers show larger degradation in word-line to sense amplifier enable (SAE) delay ( $\text{T}_{\mathrm{ WS}}$ ) and sense amplifier sensing delay ( $\text{T}_{\mathrm{ SA}}$ ) compared with the SOI counterparts. Using WL to SAE self-timed sensing scheme mitigates the BTI induced delay degradation. A new reliability-tolerant sense amplifier with speed-up design is proposed for the first time to improve the PBTI dominated sensing delay for UTB GeOI sense amplifier.