This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

A fast and unconditionally stable maximum power point tracking scheme with high tracking efficiency is proposed for photovoltaic generators. The fast dynamics and all range stability are attained by a sliding mode control and the high tracking efficiency by a maximum power point algorithm with fine step. In response to a sudden change in radiation, our experiments show a typical convergence time of 15 ms. This is the fastest convergence time reported to date. In addition we demonstrate stable convergence all across the photovoltaic curve, from short-circuit to open-circuit. The theory is validated experimentally.

Maximum Power Point Tracking Employing Sliding Mode Control

Coupled inductors can create multiple resonant frequencies in a compact high-order resonator. Together with proper nonlinear active circuitry, such a high-order resonator realizes a multi-mode oscillator covering a wide frequency range. Compared with conventional switched-resonator-based approaches that consume the same chip area, the proposed coupled-inductor-based resonator results in larger quality-factor, and hence, lower oscillator phase noise. In the proposed multi-mode oscillator that uses the multi-port coupled inductors, mode switching is achieved using independent active cores without using lossy switches in the resonator path. The behavior of the multi-mode resonator as a multi-port network in an oscillator, design trade-offs, and switching transient response of the multi-mode oscillator have been studied analytically. As a proof of concept, an integrated voltage-controlled oscillator (VCO) with a 1.28-6.06 GHz tuning range is designed and fabricated in a 0.13 mum CMOS technology. The triple-mode VCO uses a sixth-order resonator based on three coupled inductors with a compact common-centric layout. Depending on the oscillation frequency, the VCO current consumption is automatically adjusted from 2.9 to 6.1 mA to achieve a low phase noise throughout the frequency range. The measured phase noises at 1 MHz offset from carrier frequencies of 1.76, 2.26, 3.3, 4.5, and 5.6 GHz are -119.3 , -120.15 , -118.1 , -117 , and -113.5 dBc/Hz , respectively. The chip area, including the pads, is 1 mm times 1 mm and the supply voltage is 1.5 V.

Wideband Multi-Mode CMOS VCO Design Using Coupled Inductors

This work presents complete analysis of both one- port and two-port dual-band oscillators using transformer-based fourth-order LC tanks, from which critical parameters including oscillation frequency, start-up condition, tank Q, phase noise-are thoroughly derived and compared. It is shown that one-port oscillators consume less power than two-port counterparts but may suffer from stability problem which can be solved by a notch-peak cancellation technique. On the other hand, compared to one-port oscillators, two-port oscillators need to consume more power to obtain the same output swing, but their phase noise can be improved more linearly with increasing bias current, and thus they can achieve lower phase noise with a sufficiently large bias current. Based on the results, a dual-band quadrature voltage- controlled oscillator (Q-VCO) is systematically designed and implemented in a 0.13- m CMOS process for software-defined -radio (SDR) applications, in which the two-port topology is used in the low band for low phase noise and the one-port topology is employed in the high band for low power consumption. The prototype achieves a dual-band operation with in-phase and quadrature-phase (IQ) output signals from 2.7 GHz to 4.3 GHz and from 8.4 GHz to 12.4 GHz. At 3.6 GHz and 10.4 GHz, phase noise at 3 MHz offset of dBc/Hz and dBc/Hz and sideband-rejection ratios (SBR) of 37 dB and 41 dB are measured, respectively.

Analysis and Design of Transformer-Based Dual-Band VCO for Software-Defined Radios

A new fully integrated, dual-band CMOS voltage controlled oscillator (VCO) is presented. The VCO is composed of n-core cross-coupled Colpitts VCOs and was implemented in 0.18 mum CMOS technology with 0.8 V supply voltage. The circuit allows the VCO to operate at two resonant frequencies with a common LC tank. The VCO has two control inputs, one for continuous control of the output frequency and one for band switching. This VCO is configured with 5 GHz and 12 GHz frequency bands with differential outputs. The dual-band VCO operates in 4.78-5.19 GHz and 12.19-12.61 GHz. The phase noises of the VCO operating at 5.11 and 12.2 GHz are -117.16 dBc/Hz and -112.15 dBc/Hz at 1 MHz offset, respectively, while the VCO draws 3.2/2.72 mA and 2.56/2.18 mW consumption at low/high frequency band from a 0.8 V supply.

A Dual-Band CMOS Voltage-Controlled Oscillator Implemented With Dual-Resonance LC Tank

A quasi-monolithic voltage-tunable film bulk acoustic resonator (FBAR) enhanced oscillator for 2.1 GHz in 0.25-mum SiGe BiCMOS technology is designed, fabricated, and evaluated. The narrow-band FBAR was built above the SiGe circuit through later Si post-processing steps. The oscillator is based on a two-transistor loop structure and uses two resonators, namely a parallel LC tank and an above-IC FBAR in its series-resonant mode. The improvement in phase noise performance is significant compared to a similar reference LC voltage-controlled oscillator (VCO), with the best phase noise being -144.1 dBc/Hz at an offset of 1 MHz and -149.6 dBc/Hz at 3 MHz. The architecture offers advantages in overcoming frequency tuning difficulties usually present when using high-Q resonators. Although the width of the tuning range comes at some cost on phase noise, the measured performance satisfies contemporary wireless standards such as GPS

Novel VCO Architecture Using Series Above-IC FBAR and Parallel LC Resonance

A dual-band LC voltage-controlled oscillator (VCO) architecture suitable for GSM/PCS/DCS applications is presented. The VCO utilizes a fourth-order resonance tank and avoids quality-factor-deteriorating switches. The paper outlines the design tradeoffs and the VCO when using a fourth-order resonator. The 0.8-GHz/1.8-GHz test chip was fabricated in the 0.5-mum IBM-5AM SiGe process and has achieved phase noise of -134 dBc/Hz at a 1-MHz frequency offset from the carrier, with 56-MHz and 121-MHz tuning ranges in the corresponding bands. The VCO core consumes 15 mW from a 2.5-V power supply

Dual-Band LC VCO Architecture With a Fourth-Order Resonator

The traditional approach to simulate ungrounded inductors in active gyrator filters uses two gyrators with all equal transconductances. However, this paper shows that the differences between gyrator transconductances can be employed to obtain certain advantages. The filter can be designed with extra gain and with different terminating resistors, but without need of any additional buffer amplifiers. These advantages are achieved by using an appropriate theoretical model of the gyrator simulated floating inductance in the filter design process. The model separates the simulated inductance from the amplification, thus suggesting more flexible filter design. Further the model is extended to reflect also some OTA imperfections-their input and output impedances and their noise generation. In addition, the discussed model gives a unified approach for theoretical analysis of gyrator LC filters with floating inductors.

Theoretical Model of Ungrounded Inductance Realized With Two Gyrators

A theoretical analysis of the constraints posed by a tapped inductor on a dual-band fourth-order voltage-controlled oscillator (VCO) is presented. The analysis provides guidelines for frequency band selection, tapped-inductor design, and VCO optimization. The guidelines are utilized in a VCO design example simulated on a 45-nm CMOS process. An adaptive frequency-tuning scheme exploits unique features of the fourth-order tank to optimize VCO performance.

Design Considerations in Tapped-Inductor Fourth-Order Dual-Band VCO

The effect of an amplitude diode limiter on the oscillating conditions and frequency of oscillation of a 2.7 GHz series resonance LC-VCO, designed on Spectre-Cadence and implemented on 0.25 /spl mu/m BiCMOS process of Bell Labs, Lucent Microelectronics, is analysed by semi-symbolic analysis (SSA). The results show the value of the diode dynamic resistance needed and the resulting changes in the oscillating frequency.

I.S. Uzunov

Papers

Novel VCO Architecture Using Series Above-IC FBAR and Parallel LC Resonance

Dual-Band LC VCO Architecture With a Fourth-Order Resonator

Theoretical Model of Ungrounded Inductance Realized With Two Gyrators

Design Considerations in Tapped-Inductor Fourth-Order Dual-Band VCO

Semi-symbolic analysis (SSA) for amplitude control design of series resonance low-voltage VCO