In silicon nanocrystal based metal–oxide–semiconductor memory structures, tuning of the electron tunneling distance between the Si substrate and Si nanocrystals located in the gate oxide is a crucial requirement for the pinpointing of optimal device architectures. In this work it is demonstrated that this tuning of the “injection distance” can be achieved by varying the Si+ ion energy or the oxide thickness during the fabrication of Si nanocrystals by ultralow-energy silicon implantation. Using an accurate cross-section transmission electron microscopy (XTEM) method, it is demonstrated that two-dimensional arrays of Si nanocrystals cannot be positioned closer than 5 nm to the channel by increasing the implantation energy. It is shown that injection distances down to much smaller values (2 nm) can be achieved only by decreasing the nominal thickness of the gate oxide. Depth profiles of excess silicon measured by time-of-flight secondary ion mass spectroscopy and Si nanocrystal locations determined by XTEM are compared with Monte-Carlo simulations of the implanted Si profiles taking into account dynamic target changes due to ion implantation, ion erosion, and ion beam mixing. This combination of experimental and theoretical studies gives a safe explanation regarding the unique technological route of obtaining Si nanocrystals at distances smaller than 5 nm from the channel: the formation of nanocrystals requires that the interface mixing due to collisional damage does not overlap with the range profile to the extent that there is no more a local maximum of Si excess buried in the SiO2 layer.

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Manipulation of two-dimensional arrays of Si nanocrystals embedded in thin SiO2 layers by low energy ion implantation

Binary collision simulations of high-fluence 1 keV Si+ ion implantation into 8-nm-thick SiO2 films on (001)Si were combined with kinetic Monte Carlo simulations of Si nanocrystal (NC) formation by phase separation during annealing. For nonvolatile memory applications, these simulations help to control the size and location of NCs. For low concentrations of implanted Si, NCs form via nucleation, growth, and Ostwald ripening, whereas for high concentrations Si separates by spinodal decomposition. In both regimes, NCs form above a thin NC free-oxide layer at the SiO2/Si interface. This, self-adjusted layer has just a thickness appropriate for NC charging by direct electron tunneling. Only in the nucleation regime the width of the tunneling oxide and the mean NC diameter remain constant during a long annealing period. This behavior originates from the competition of Ostwald ripening and Si loss to the Si/SiO2 interface. The process simulations predict that, for nonvolatile memories, the technological demands ...

Size and location control of Si nanocrystals at ion beam synthesis in thin SiO2 films

We investigated the dependence of implantation dose on the charge storage characteristics of large-area n-channel metal–oxide–semiconductor field-effect transistors with 1-keV Si+-implanted gate oxides. Gate bias and time-dependent source–drain current measurements are reported. Devices implanted with 1×1016 cm−2 Si dose exhibit a continuous (trap-like) charge storage process under both static and dynamic conditions. In contrast, for 2×1016 cm−2 implanted devices, electrons are stored in Si nanocrystals in discrete units at low gate voltages, as revealed by a periodic staircase plateau of the source–drain current with a low gate voltage sweep rate, and the step-like decrease of the time-dependent monitoring of the channel current. These observations of room-temperature single-electron storage effects support the pursuit of large-area devices operating on the basis of Coulomb blockade phenomena.

Room-temperature single-electron charging phenomena in large-area nanocrystal memory obtained by low-energy ion beam synthesis

Silicon dioxide (SiO2) on Si layers with embedded germanium nanocrystals (Ge-ncs) were fabricated using Ge+ implantation and subsequent annealing. Transmission electron microscopy and Rutherford backscattering spectrometry have been used to study the Ge redistribution in the SiO2 films as a function of annealing temperature. A monolayer of Ge-ncs near the Si∕SiO2 interface was formed under specific annealing conditions. This layer, with a nc density and mean size measured to be, respectively, 1.1×1012∕cm2 and 5nm, is located at approximately 4nm from the Si∕SiO2 interface. Capacitance–voltage measurements were performed on metal-oxide-semiconductor structures containing such implanted SiO2 layers in order to study their electrical properties. The results indicate a strong memory effect at relatively low programming voltages (<5V) due to the presence of Ge-ncs near the Si∕SiO2 interface.

Structural and electrical properties of ge nanocrystals embedded in SiO2 by ion implantation and annealing

The effect of thermal treatments in nitrogen-diluted oxygen on the structural characteristics of two-dimensional arrays of Si nanocrystals (NCs) fabricated by ultralow-energy ion implantation (1 keV) in thin silicon dioxide layers is reported. The NC characteristics (size, density, and coverage) have been measured by spatially resolved electron-energy-loss spectroscopy by using the spectrum-imaging mode of a scanning transmission electron microscope. Their evolution has been studied as a function of thermal treatment duration at a temperature (900 °C) below the SiO2 viscoelastic point. An extended spherical Deal-Grove [J. Appl. Phys. 36, 3770 (1965)] model for self-limiting oxidation of embedded silicon NCs has been carried out. It proposes that the stress effects, due to oxide deformation, slow down the NC oxidation rate and lead to a self-limiting oxide growth. The model predictions show a good agreement with the experimental results. Soft oxidation appears to be a powerful way for manipulating the NC s...

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Oxidation of Si nanocrystals fabricated by ultralow-energy ion implantation in thin SiO2 layers

The structure evolution of annealed low-energy Si- or Ge-implanted thin and thick SiO2 layers is studied. The majority of Si (or Ge) species is restricted within a 3–4 nm thick layer. Si is able to separate and crystallize more easily than Ge. The glass transition temperature of the as-implanted structure has a significant effect on the progress of phase transformations accompanying annealing.

Formation of 2-D arrays of semiconductor nanocrystals or semiconductor-rich nanolayers by very low-energy Si or Ge ion implantation in silicon oxide films

Thin Si02 films have been implanted with Ge+ ions and subsequently annealed. Transmission electron microscopy results indicate that after annealing at 95()oC Ge remains distributed in a band and not in separate pockets. The charge storage effects of the Ge-implanted gate oxide of MaS capacitors have been studied for accumulation conditions through J-V and C-V measurements. A high positive' voltage pulse leads to a positive shift . of the capacitance-voltage curve, while a low positive voltage stress results in a small negative drift. The jlatband voltage (V FlY shift mechanism is attributed to the trap­ like behaviour of the implanted Ge.

http://ieeexplore.ieee.org/iel5/10061/32274/01505532.pdf

J. Gautier

Papers

Formation of 2-D arrays of semiconductor nanocrystals or semiconductor-rich nanolayers by very low-energy Si or Ge ion implantation in silicon oxide films

Structure and Memory Effects of Low Energy Ge-Implanted Thin SiO2 Films