A novel approach to filter design, based on Adams' [1] ‘log-domain’ filters, is proposed that yields a truly current-mode circuit realisation. Adams' idea, which was introduced in a limited context, is generalised to permit a complete distortionless synthesis procedure, which results in circuit implementations readily realisable using complementary bipolar processes. It is shown that, by introducing an exponential map on the state-space description of the desired linear system, a log-domain filter can be fully realised with transistors configured in current mirror-type groupings, current sources and capacitors. Owing to the mapping, the state variables are intrinsically related to current, and not voltage, in the resulting circuits, a fact that emphasises the current-mode nature of the design. A general biquadratic filter section is designed, and, following discussion of cascading sections, a seventh-order Chebychev lowpass filter is designed. All designed circuits are shown to be tunable over a two-decade range in frequency while their characteristics are accurately preserved, even for biquad sections whose f0Q product is greater than fT/10. The Chebychev filter is shown in simulation to possess nearly 60 dB dynamic range relative to 0.9% THD, with a cutoff frequency of nearly 5 MHz, using transistor models from AT&T's CBIC-R 300 MHz complementary bipolar process.

Log-domain filtering: an approach to current-mode filtering

Novel CMOS realisations of a differential voltage current conveyor (DVCC) are described. These circuits are powerful building blocks, especially for applications demanding differential or floating inputs like impedance converter circuits and current mode instrumentation amplifiers. Applications suitable for VLSI are then considered by using the DVCC to realise a MOS transconductor and a continuous-time current mode MOSFET-C filter. PSpice simulations indicate the excellent performance of the proposed DVCC and of its circuit applications.

Novel CMOS differential voltage current conveyor and its applications

The state of the art of continuous-time filter design is reviewed Several techniques are discussed and compared in terms of performance and implementation feasibility in different fabrication technologies This review does not aim at historical completeness, but rather emphasizes techniques that have proven their worth in commercial applications Brief mention is also made of experimental work which, in the opinion of the author, shows promise for the future >

Integrated continuous-time filter design /spl minus/ an overview

A new method of analog filter design is proposed where nonlinear active components are a natural part of a filter realizing an overall linear transfer function. This approach to design is articulated in the generation of the class of so-called "Exponential State Space" (ESS) filters. An outgrowth of "log filters", ESS filters are created via a mapping on the state space of a linear filter. Specifically, the state variables are equal to simple functions of exponentials or node voltages. The use of exponential, hyperbolic tangent, and hyperbolic sine mappings is shown to produce realizable nodal equations that result in "log", "tanh" and "sinh" filters, respectively. Aspects of interpretation and realization of the transformed state equations are discussed. It is shown that sinh filters are class AB filters, which is an intriguing extension of a concept introduced by Seevinck (1990). The different filter types are compared to an analogous standard transconductance-C filter via simulation of a band-pass filter with a Q of 5. All filters demonstrate tunability over a 100 to 1 range with excellent frequency response stability and accuracy over the tuning range, which extends to 5 MHz. These results and IMD and noise performance are given using both ideal transistors and transistors whose cutoff frequency equals approximately 300 MHz.

Exponential state space filters: a generic current mode-design strategy

The requirements for good MOSFET modeling are discussed, as they apply to usage in analog and mixed analog-digital design. A set of benchmark tests that can be easily performed by the reader are given, and it is argued that most CAD models today cannot pass all the tests, even for simple, long-channel devices at room temperature. A number of other problems are discussed, and in certain cases specific cures are suggested. The issue of parameter extraction is addressed. Finally, the context of model development and usage is considered, and it is argued that some of the factors responsible for the problems encountered in the modeling effort are of a nontechnical nature. >

MOSFET modeling for analog circuit CAD: problems and prospects

Design considerations are presented for attaining accurate output balancing in fully differential operational amplifiers over the useful operating frequency of the differential signals. Such output balancing is obtained by merging the common-mode feedback and the differential gain paths as close to the front end of the amplifier as possible, ensuring maximum sharing of circuit components. Two circuit designs implemented in a 5-V, 1.75- mu m process are presented, one based on a two-stage topology and one based on a folded cascode topology. Experimental results for both designs are given. >

Fully differential operational amplifiers with accurate output balancing

A fifth-order CMOS continuous-time Bessel filter with a tunable 6- to 15-MHz cutoff frequency is described. This fully balanced transconductance-capacitor (G/sub m/-C) leapfrog filter achieves a dynamic range of 55 dB while dissipating 96 mW in a 5-V 0.9- mu m CMOS process. The author reviews the disk drive application and filtering requirements, and explains why the G/sub m/-C continuous-time filtering approach was used. The on-chip master-slave tuning system uses a voltage-controlled oscillator (VCO). Experimental results are presented. >

Design of a 15-MHz CMOS continuous-time filter with on-chip tuning

A complete read channel device using PR-IV signalling and maximum likelihood detection is described. Descriptions, simulated performance and measured results of the digital adaptive feedback loops (AGC, FIR tap weights, DFE tap weights, frequency and phase) in the read channel are presented. Analog FIR filter and hash A/D converter performance is presented. The weighted averaging servo demodulation technique used in the device is described and compared to integration. This monolithic CMOS device consumes less than 0.75 W when reading at 85 Mbps, and occupies a step-and-repeat area of 24.6 mm/sup 2/. >

A high speed, low power PRML read channel device

The design of a high-performance integrating servo demodulator circuit for hard disk-drive systems is described. This design implements a filter, demodulation of the normal and quadrature position error signals, off-track detector, and servo timing. The operating frequency range is 1 MHz to 6 MHz with pulse width (PW50) variation from 60 ns to 180 ns. The servo has a dedicated AGC (automatic gain control) loop with a 15-dB range. The linearity of the position error signal output is better than 3%. The circuits are implemented in 0.9-/spl mu/m CMOS technology.

https://ieeexplore.ieee.org/iel2/4489/12733/00590691.pdf

An integrating servo demodulator for hard disk drives

Two MOS squarer circuits are presented. One implementation operates on sampled-data signals, while the second uses continuous-time operation. Both squarers achieve the square-law function with MOS transistors operating in the nonsaturation region biased with zero drain-to-source voltage. Benefits of nonsaturated operation are discussed. The sampled-data squarer is practically independent of component mismatches and clock pulse-width mismatches. >

J.M. Khoury

Papers

Fully differential operational amplifiers with accurate output balancing

Design of a 15-MHz CMOS continuous-time filter with on-chip tuning

A high speed, low power PRML read channel device

An integrating servo demodulator for hard disk drives

Sampled-data and continuous-time squarers in MOS technology