We report on a GaN metal-oxide-semiconductor high-electron-mobility-transistor (MOS-HEMT) using atomic-layer-deposited (ALD) Al2O3 as the gate dielectric. Compared to a conventional GaN high-electron-mobility-transistor (HEMT) of similar design, the MOS-HEMT exhibits several orders of magnitude lower gate leakage and several times higher breakdown voltage and channel current. This implies that the ALD Al2O3∕AlGaN interface is of high quality and the ALD Al2O3∕AlGaN∕GaN MOS-HEMT is of high potential for high-power rf applications. In addition, the high-quality ALD Al2O3 gate dielectric allows the effective two-dimensional (2D) electron mobility at the AlGaN∕GaN heterojunction to be measured under a high transverse field. The resulting effective 2D electron mobility is much higher than that typical of Si, GaAs or InGaAs metal-oxide-semiconductor field-effect-transistors (MOSFETs).

GaN metal-oxide-semiconductor high-electron-mobility-transistor with atomic layer deposited Al2O3 as gate dielectric

The review evaluates thresholds of peripheral nerve stimulation by complex current waveforms. A neuroelectric model employing Frankenhaeuser-Huxley membrane nonlinearities is used to derive excitation thresholds for monophasic and biphasic pulse sequences, as well as sinusoidal stimuli. The model, along with principles of magnetic field induction, is used to derive criteria of acceptability for exposure to time-varying magnetic fields. Applications to pulsed gradient fields from magnetic resonance imaging devices are discussed.

Peripheral nerve stimulation by induced electric currents: exposure to time-varying magnetic fields.

An NMOS voltage reference has been developed that exhibits extremely low drift with temperature. The reference is based on the difference between the gate/source voltages of enhancement and depletion-mode NMOS transistors. The theoretical dependence of the reference voltage on both device and circuit parameters is analyzed and conditions for optimal performance are derived. The reference NMOS transistors are biased to the optimizing current levels by a unique feedback circuit. The measured output voltage drift in the integrated realization agrees well with theory and is less than 5 parts per million per degree Celsius over the temperature range -55/spl deg/ to +125/spl deg/C.

A new NMOS temperature-stable voltage reference

A new n-channel silicon MOS transistor is described that can be fabricated with channel lengths of less than 1 µ by using a double-diffusion process similar to that used in bipolar transistor fabrication. The dimensional tolerances are not tighter than those used in the processing of conventional MOS transistors. This device (called D-MOST) shows gain in the GHz range and a noise figure comparable to that of microwave transistors. The f max is 10 GHz and the noise figure is 4.0 dB at 1 GHz. A brief theory of the D-MOST is followed by the design considerations for a discrete microwave device. Results from s-parameter measurements in the range of 0.1-2.5 GHz are presented along with graphs showing the gains and the stability factor. A simple equivalent circuit is derived from the measurements. Applications of the D-MOST are described.

D-MOS transistor for microwave applications

Recently, significant progress has been made on GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) using atomic-layer deposition (ALD)-grown Al2O3 as gate dielectric. We show here that further improvement can be achieved by inserting a thin In0.2Ga0.8As layer as part of the channel between Al2O3 and GaAs channel. A 1-μm-gate-length, depletion-mode, n-channel In0.2Ga0.8As/GaAs MOSFET with an Al2O3 gate oxide of 160 A shows a gate leakage current density less than 10−4 A/cm2, a maximum transconductance ∼105 mS/mm, and a strong accumulation current at Vgs>0 in addition to buried-channel conduction. Together with longer gate-length devices, we deduce electron accumulation surface mobility for In0.2Ga0.8As as high as 660 cm2/V s at Al2O3/In0.2Ga0.8As interface.

Depletion-mode InGaAs metal-oxide-semiconductor field-effect transistor with oxide gate dielectric grown by atomic-layer deposition

A dc model is-presented for the ion-implemented silicon-gate depletion-mode IGFET from which the device terminal behavior can be determined. The device equations are derived based on the concept of a finite semiconductor capacitance in the channel region whereby the depth of the implanted channel is taken into account. The model parameter is shown to be easily measurable experimentally. The validity of the resulting model is demonstrated by showing good agreement between calculated and measured results obtained from fabricated devices, It is believed that this model lends itself well to the circuit design problem using depletion mode IGFET's.

Modeling of an ion-implanted silicon-gate depletion-mode IGFET

Performance enhancement of CMOS inverters at room and liquid-nitrogen temperatures are studied. The extent of delay improvement at low temperature is limited by the velocity saturation effect, as the channel lengths are decreased and/or the supply voltage increased. An analytical delay model taking into account velocity saturation is developed that accurately predicts the measured delay of CMOS inverter chains with drawn channel lengths down to 0.5 µm, Compared are the relative merits of CMOS devices operating at 77 K and those scaled for room-temperature operations.

Switching characteristics of scaled CMOS circuits at 77 K

An analytical snapback model for n-channel silicon-on-insulator (SOI) transistors with body either tied to the source or floating is been presented. The snapback is modeled as a nonlinear feedback system leading to negative transconductances from which the jump in current can occur at the point of instability. The crux of this model is based on the strong dependence of the transistor threshold voltage on the body potential when the body potential is above the transistor surface potential at strong inversion. No parasitic bipolar action is invoked to account for the snapback phenomena. The model correctly predicts the occurrence of hysteresis/latch phenomena and the conditions under which the current jump occurs despite some gross approximations in the electric field and the injection level. Results obtained from this model show good agreement with experimental data measured from SIMOX devices fabricated on 0.3- mu m epi film. >

An analytical model for snapback in n-channel SOI MOSFET's

The snapback effect is usually observed in the output characteristics of an n-channel SOI MOSFET with zero gate voltage in which the drain-to-source breakdown voltage is less than the drain-to-body avalanche voltage. It can be attributed to parasitic lateral bipolar actions as well as the MOS feedback mode of operation-a point often overlooked in the literature. An analytical model is developed for predicting the observed output characteristics taking into account both the bipolar and the MOS mechanisms. Results obtained from this model agree well with the experimental I-V curves, and show that, with continuing scaling of device geometries and improvement in SOI materials, the bipolar-induced snapback will become dominant in the future. >

Modeling of output snapback characteristics in n-channel SOI MOSFETs

Recently, the depletion-type IGFET became widely used as a load device in logic circuits. The purpose of this correspondence is to present a development of the current-voltage characteristic of a depletion-type IGFET based on the assumption that the non-linear semiconductor capacitance can be replaced by a constant average capacitance. This approximation is justified in light of the theoretical and experimental results obtained by many authors [1]-[4], indicating that the exact form of the semiconductor capacitance has little effect on the dc characteristics of a field-effect device.

J.S.T. Huang

Papers

Modeling of an ion-implanted silicon-gate depletion-mode IGFET

Switching characteristics of scaled CMOS circuits at 77 K

An analytical model for snapback in n-channel SOI MOSFET's

Modeling of output snapback characteristics in n-channel SOI MOSFETs

Characteristics of a depletion-type IGFET