J
James Chen
Researcher at TSMC
Publications - 5
Citations - 65
James Chen is an academic researcher from TSMC. The author has contributed to research in topics: Wetting & Wafer. The author has an hindex of 4, co-authored 5 publications receiving 62 citations.
Papers
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Patent
Method of making tall flip chip bumps
TL;DR: In this article, a method of making electrically conductive bumps of improved height on a semiconductor device was proposed, which includes steps of depositing an under-bump metallurgy over the semiconductor devices onto a contact pad, depositing and patterning a photoresist layer to provide an opening over the under bump metallomics, and depositing a first electricallyconductive material into the opening in the photoresists layer, removing the second electrically conducting material over the first electrifying material, applying a flux agent to the top surface of the second
Patent
Method for removing solder bodies from a semiconductor wafer
TL;DR: In this article, a method for removing a multiplicity of solder bodies connected to a semiconductor wafer through a copper wetting layer from the semiconductor Wafer is disclosed.
Proceedings ArticleDOI
A new saw-like self-recovery of interface states in nitride-based memory cell
TL;DR: In this article, a self-recovery self-aligned-nitride (SAN) memory cell is proposed and fabricated in 28nm high-k metal gate (HKMG) CMOS process for high-density logic NVM applications.
Patent
Patterned conductor layer pasivation method with dimensionally stabilized planarization
TL;DR: In this paper, a planarizing passivation layer is formed upon a dimensionally stabilizing layer, which is then attenuated within a thermally annealed planarising passivated layer replication of the topographic variation at the periphery of the patterned conductor layer.
Journal ArticleDOI
On-Chip Recovery Operation for Self-Aligned Nitride Logic Non-Volatile Memory Cells in High-K Metal Gate CMOS Technology
Po-Yen Lin,Yu-Lun Chiu,Yuh-Te Sung,James Chen,Tzong-Sheng Chang,Ya-Chin King,Chrong Jung Lin +6 more
TL;DR: In this article, a new on-chip recovery operation is proposed in the self-aligned nitride (SAN) cell, where the merged nitride spacer is sandwiched between high-k metal gate stacks in nano-meter CMOS process.