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Po-Yen Lin

Researcher at National Tsing Hua University

Publications -  12
Citations -  62

Po-Yen Lin is an academic researcher from National Tsing Hua University. The author has contributed to research in topics: CMOS & Ingredient. The author has an hindex of 4, co-authored 10 publications receiving 44 citations.

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Journal ArticleDOI

Phase-Changeable Nanoemulsions for Oral Delivery of a Therapeutic Peptide: Toward Targeting the Pancreas for Antidiabetic Treatments Using Lymphatic Transport

TL;DR: An oil‐structured nanoemulsion system that consists of a phase‐changeable fatty acid that allows EXT to be delivered orally and absorbed efficiently in the small intestine and significantly improve the bioavailability of EXT via intestinal lymphatic transport, ultimately accumulating in the pancreas, suggesting the possibility of orally delivering labile peptide drugs.
Proceedings ArticleDOI

A new saw-like self-recovery of interface states in nitride-based memory cell

TL;DR: In this article, a self-recovery self-aligned-nitride (SAN) memory cell is proposed and fabricated in 28nm high-k metal gate (HKMG) CMOS process for high-density logic NVM applications.
Journal ArticleDOI

Effect of three-dimensional current distribution on characterizing parasitic resistance of FinFETs

TL;DR: In this paper, a thorough analysis of the FinFET resistance and current distribution is presented by combining multiple conventional and novel measurement techniques, and the key components that contribute to the parasitic resistance of Fin-FETs can be quantified.
Journal ArticleDOI

Self-Matching SRAM With Embedded OTP Cells in Nanoscale Logic CMOS Technologies

TL;DR: In this article, a new static RAM (SRAM) cell featuring self-matching characteristic for enhanced static noise margin (SNM) in lowvoltage applications is reported.
Journal ArticleDOI

On-Chip Recovery Operation for Self-Aligned Nitride Logic Non-Volatile Memory Cells in High-K Metal Gate CMOS Technology

TL;DR: In this article, a new on-chip recovery operation is proposed in the self-aligned nitride (SAN) cell, where the merged nitride spacer is sandwiched between high-k metal gate stacks in nano-meter CMOS process.