Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

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Fundamentals of Modern VLSI Devices

http://www.acsu.buffalo.edu/~jmjornet/papers/2014/j1.pdf

Full length article: Terahertz band: Next frontier for wireless communications

Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling.

CMOS scaling into the nanometer regime

The decade of the 1990's is an opportune time for scientists and engineers to create cost-effective silicon "superchips" that merge silicon photonics with advanced silicon electronics on a silicon substrate. We can expect significant electrooptical devices from Column IV materials (Si, Ge, C and Sn) for a host of applications. The best devices will use strained-layer epitaxy, doped heterostructures, and bandgap engineering of quantum-confined structures. This paper reviews Si-based photonic components and optoelectronic integration techniques, both hybrid and monolithic. >

Silicon-based optoelectronics

A method of forming an integrated circuit using an amorphous carbon film. The amorphous carbon film is formed by thermally decomposing a gas mixture comprising a hydrocarbon compound and an inert gas. The amorphous carbon film is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the amorphous carbon film is used as a hardmask. In another integrated circuit fabrication process, the amorphous carbon film is an anti-reflective coating (ARC) for deep ultraviolet (DUV) lithography. In yet another integrated circuit fabrication process, a multi-layer amorphous carbon anti-reflective coating is used for DUV lithography.

Method of depositing an amorphous carbon layer

The fabrication of silicon heterojunction bipolar transistors which have a record unity-current-gain cutoff frequency (f/sub T/) of 75 GHz for a collector-base bias of 1 V, an intrinsic base sheet resistance (R/sub bi/) of 17 k Omega / Square Operator , and an emitter width of 0.9 mu m is discussed. This performance level, which represents an increase by almost a factor of 2 in the speed of a Si bipolar transistor, was achieved in a poly-emitter bipolar process by using SiGe for the base material. The germanium was graded in the 45-nm base to create a drift field of approximately 20 kV/cm, resulting in an intrinsic transit time of only 1.9 ps. >

75-GHz f/sub T/ SiGe-base heterojunction bipolar transistors

A detailed review of SiGe epitaxial base technology is presented, which chronicles the progression of research from materials deposition through device and integration demonstrations, culminating in the first SiGe integrated circuit application. In part I of this paper, the requirements and processes for high-quality SiGe film preparation are discussed, with emphasis on fundamental principles. A detailed overview of SiGe HBT device design and implications for circuit applications is then presented. >

Si/SiGe epitaxial-base transistors. I. Materials, physics, and circuits

For pt. I, see ibid., vol. 3, p. 455-68 (1995). This part focuses on process integration concerns, first described in general terms and then detailed through an extensive review of both simple non-self-aligned device structures and more complex self-aligned device structures. The extension of SiGe device technology to high levels of integration is then discussed through a detailed review of a full SiGe HBT BiCMOS process. Finally, analog circuit design is discussed and concluded, with a description of a 12-bit Digital-to-Analog Converter presented to highlight the current status of SiGe technology. >

Si/SiGe epitaxial-base transistors. II. Process integration and analog applications

Recent advances in thin film growth techniques, notably the maturation of low temperature silicon epitaxy, have enabled the routine fabrication of highly controlled dopant and silicon:germanium alloy profiles. These capabilities, combined with refinements in heterojunction bipolar transistor designs, have led to the first integrated circuits in the silicon:germanium materials system. Utilizing a commercial (Leybold-AG) UHVCVD tool for SiGe epitaxy on a standard 8" CMOS line, medium scale integration has been achieved, with the first IC components being SiGe HBT based 1 Ghz, 12 bit, digital to analog converters.

Silicon:germanium heterojunction bipolar transistors: from experiment to technology

Noble metal plating on a preexisting seed layer is used in the fabrication of electrodes for DRAM and FRAM. The plating may be spatially selective or nonselective. In the nonselective case, a blanket film is first plated and then patterned after deposition by spatially selective material removal. In the selective case, the plated deposits are either selectively grown in lithographically defined areas by a through-mask plating technique, or selectively grown as a conformal coating on the exposed regions of a preexisting electrode structure. A diamond-like carbon mask can be used in the plating process. A self-aligned process is disclosed for selectively coating insulators in a through-mask process.

James H. Comfort

Papers

75-GHz f/sub T/ SiGe-base heterojunction bipolar transistors

Si/SiGe epitaxial-base transistors. I. Materials, physics, and circuits

Si/SiGe epitaxial-base transistors. II. Process integration and analog applications

Silicon:germanium heterojunction bipolar transistors: from experiment to technology

Plating of noble metal electrodes for DRAM and FRAM