Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption. >

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Low-power CMOS digital design

Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

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Fundamentals of Modern VLSI Devices

Point defects and impurities strongly affect the physical properties of materials and have a decisive impact on their performance in applications. First-principles calculations have emerged as a powerful approach that complements experiments and can serve as a predictive tool in the identification and characterization of defects. The theoretical modeling of point defects in crystalline materials by means of electronic-structure calculations, with an emphasis on approaches based on density functional theory (DFT), is reviewed. A general thermodynamic formalism is laid down to investigate the physical properties of point defects independent of the materials class (semiconductors, insulators, and metals), indicating how the relevant thermodynamic quantities, such as formation energy, entropy, and excess volume, can be obtained from electronic structure calculations. Practical aspects such as the supercell approach and efficient strategies to extrapolate to the isolated-defect or dilute limit are discussed. Recent advances in tractable approximations to the exchange-correlation functional ($\mathrm{DFT}+U$, hybrid functionals) and approaches beyond DFT are highlighted. These advances have largely removed the long-standing uncertainty of defect formation energies in semiconductors and insulators due to the failure of standard DFT to reproduce band gaps. Two case studies illustrate how such calculations provide new insight into the physics and role of point defects in real materials.

First-principles calculations for point defects in solids

Understanding energy dissipation and transport in nanoscale structures is of great importance for the design of energy-efficient circuits and energy-conversion systems. This is also a rich domain for fundamental discoveries at the intersection of electron, lattice (phonon), and optical (photon) interactions. This review presents recent progress in understanding and manipulation of energy dissipation and transport in nanoscale solid-state structures. First, the landscape of power usage from nanoscale transistors (∼10−8 W) to massive data centers (∼109 W) is surveyed. Then, focus is given to energy dissipation in nanoscale circuits, silicon transistors, carbon nanostructures, and semiconductor nanowires. Concepts of steady-state and transient thermal transport are also reviewed in the context of nanoscale devices with sub-nanosecond switching times. Finally, recent directions regarding energy transport are reviewed, including electrical and thermal conductivity of nanostructures, thermal rectification, and the role of ubiquitous material interfaces. 
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Energy dissipation and transport in nanoscale devices

Low-resistivity p-type GaN films, which were obtained by N2-ambient thermal annealing or low-energy electron-beam irradiation (LEEBI) treatment, showed a resistivity as high as 1×106 Ωcm after NH3-ambient thermal annealing at temperatures above 600°C. In the case of N2-ambient thermal annealing at temperatures between room temperature and 1000°C, the low-resistivity p-type GaN films showed no change in resistivity, which was almost constant between 2 Ωcm and 8 Ωcm. These results indicate that atomic hydrogen produced by NH3 dissociation at temperatures above 400°C is related to the hole compensation mechanism. A hydrogenation process whereby acceptor-H neutral complexes are formed in p-type GaN films was proposed. The formation of acceptor-H neutral complexes causes hole compensation, and deep-level and weak blue emissions in photoluminescence.

https://iopscience.iop.org/article/10.1143/JJAP.31.1258/pdf

Hole Compensation Mechanism of P-Type GaN Films

The fabrication of silicon heterojunction bipolar transistors which have a record unity-current-gain cutoff frequency (f/sub T/) of 75 GHz for a collector-base bias of 1 V, an intrinsic base sheet resistance (R/sub bi/) of 17 k Omega / Square Operator , and an emitter width of 0.9 mu m is discussed. This performance level, which represents an increase by almost a factor of 2 in the speed of a Si bipolar transistor, was achieved in a poly-emitter bipolar process by using SiGe for the base material. The germanium was graded in the 45-nm base to create a drift field of approximately 20 kV/cm, resulting in an intrinsic transit time of only 1.9 ps. >

75-GHz f/sub T/ SiGe-base heterojunction bipolar transistors

A detailed review of SiGe epitaxial base technology is presented, which chronicles the progression of research from materials deposition through device and integration demonstrations, culminating in the first SiGe integrated circuit application. In part I of this paper, the requirements and processes for high-quality SiGe film preparation are discussed, with emphasis on fundamental principles. A detailed overview of SiGe HBT device design and implications for circuit applications is then presented. >

Si/SiGe epitaxial-base transistors. I. Materials, physics, and circuits

Two new experiments are presented which suggest that the ‘‘bulk‐compensating donor’’ phenomenon observed in p‐Si is probably a deactivation process of the boron acceptor by hydrogen with the formation of a B−H+ pair. The two experiments are (i) avalanche hole injection in Al‐gate metal‐oxide‐silicon capacitor from boron‐diffused n‐Si substrate and (ii) 5‐keV electron irradiation of Al/p‐Si Schottky diodes. Atomic hydrogen may be released by the avalanche injected energetic electrons or holes or keV electrons from the Al–H, AlO–H, Si–H, and SiO–H sites in the Al gate and the SiO2 film as well as at the Al/SiO2 and SiO2/Si interfaces, which may then migrate to the boron acceptor sites to form the B−H+ pair. Observed hydrogen bond breaking rate by holes is as much as two orders of magnitude larger than by electrons, which is consistent with the thermal hole capture and energetic electron impact bond‐breaking models.

Deactivation of the boron acceptor in silicon by hydrogen

For pt. I, see ibid., vol. 3, p. 455-68 (1995). This part focuses on process integration concerns, first described in general terms and then detailed through an extensive review of both simple non-self-aligned device structures and more complex self-aligned device structures. The extension of SiGe device technology to high levels of integration is then discussed through a detailed review of a full SiGe HBT BiCMOS process. Finally, analog circuit design is discussed and concluded, with a description of a 12-bit Digital-to-Analog Converter presented to highlight the current status of SiGe technology. >

Si/SiGe epitaxial-base transistors. II. Process integration and analog applications

A 0.5-µm-channel CMOS design optimized for liquid-nitrogen temperature operation is described. Thin gate oxide (12.5 nm) and dual polysilicon work functions (n+-poly gate for n-channel and p+-poly for p-channel transistors) are used. The power supply voltage is chosen to be 2.5 V based on performance, hot-carrier effects, and power dissipation considerations. The doping profiles of the channel and the background (substrate or well) are chosen to optimize the mobility, substrate sensitivity, and junction capacitance with minimum process complexity. The reduced supply voltage enables the use of silicided shallow arsenic and boron junctions, without any intentional junction grading, to control short-channel effects and to reduce the parasitic series resistance at 77 K. The same self-aligned silicide over the polysilicon gate electrode reduces the sheet resistance (as low as 1 Ω/sq at 77 K) and provides the strapping between the gates of the complementary transistors. The design has been demonstrated by a simple n-well/p-substrate CMOS process with very good device characteristics and ring-oscillator performance at 77 K.

J.Y.-C. Sun

Papers

75-GHz f/sub T/ SiGe-base heterojunction bipolar transistors

Si/SiGe epitaxial-base transistors. I. Materials, physics, and circuits

Deactivation of the boron acceptor in silicon by hydrogen

Si/SiGe epitaxial-base transistors. II. Process integration and analog applications

Submicrometer-channel CMOS for low-temperature operation