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James Patrick Robertson

Researcher at Nvidia

Publications -  8
Citations -  1989

James Patrick Robertson is an academic researcher from Nvidia. The author has contributed to research in topics: Cache pollution & Cache. The author has an hindex of 6, co-authored 8 publications receiving 1916 citations. Previous affiliations of James Patrick Robertson include Purdue University.

Papers
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Journal ArticleDOI

A Comparison of Eleven Static Heuristics for Mapping a Class of Independent Tasks onto Heterogeneous Distributed Computing Systems

TL;DR: It is shown that for the cases studied here, the relatively simple Min?min heuristic performs well in comparison to the other techniques, and one even basis for comparison and insights into circumstances where one technique will out-perform another.
Proceedings ArticleDOI

A taxonomy for describing matching and scheduling heuristics for mixed-machine heterogeneous computing systems

TL;DR: A new taxonomy for classifying mapping heuristics for HC environments is proposed (Purdue HC Taxonomy), defined in three major parts: the models used for applications and communication requests; the models use for target hardware platforms; and the characteristics of mappingHeuristics.
Book ChapterDOI

Characterizing Resource Allocation Heuristics for Heterogeneous Computing Systems

TL;DR: This chapter presents a three-part classification scheme ( 3PCS ) for HC systems that is useful for researchers who want to understand a mapper given in the literature, describe their design of a mappers more thoroughly by using a common standard, and select a mapping to match a given real-world environment.
Proceedings ArticleDOI

Generalized Cannon's algorithm for parallel matrix multiplication

TL;DR: Performance analysis shows that the proposed generalized Cannon’s algorithm (GCA) requires fewer page faults than a previously proposed algorithm (SUMMA), and it is shown that GCA maintains higher performance for large matrices than SUMMA.
Patent

Control mechanism for fine-tuned cache to backing-store synchronization

TL;DR: In this paper, the authors present a technique for processing commands received by an intermediary cache from one or more clients, where the first write command specifies a first memory address, determining that a first cache line related to a set of cache lines included in the intermediary cache is associated with the first memory addresses, causing data associated with first write commands to be written into the first cache lines, and marking the cache line as dirty.