Showing papers by "Jan Craninckx published in 2013"

A 2.1 mW 11b 410 MS/s dynamic pipelined SAR ADC with background calibration in 28nm digital CMOS

Abstract: A 410 MS/s 2x interleaved 11bit pipelined SAR ADC in 28nm digital CMOS is presented. Each ADC channel consists of a 6b coarse SAR, a dynamic residue amplifier and a 7b fine SAR and includes an on-chip calibration engine that detects and corrects comparator offsets and amplifier gain errors in the background. The ADC achieves a peak SNDR of 59.8 dB at 410 MS/s for an energy per conversion step of 6.5 fJ.

A multiband 40nm CMOS LTE SAW-less modulator with −60dBc C-IM3

Abstract: Due to the increasing demand for communication bandwidth combined with the scarceness of free spectrum, the complexity and versatility of 4th-generation modulation schemes is greater than ever. In particular, the LTE standard defines multiple RF bands and groups OFDM modulated subcarriers into Resource Blocks (RB) that can be flexibly used within the allocated channel bandwidth. When the transmitted power is concentrated in one or a few RBs, counter-intermodulation products (C-IM) may fall directly or through cross-modulation into the RX band and degrade FDD performance. They may also fall into protected bands and violate spectral emission requirements.

A 0.9V low-power 0.4–6GHz linear SDR receiver in 28nm CMOS

Abstract: Linear receivers typically use higher than standard supply voltages and consume significant power. This work presents the first 28nm CMOS multistandard receiver. Operating at just 0.9V, it tolerates 0dBm blockers and achieves +5dBm OB-IIP3, at less than 40mW and operating up to 6GHz.

A Digitally Modulated Class-E Polar Amplifier in 90 nm CMOS

Abstract: In this paper a digital amplitude modulator for a polar transmitter is presented. The instantaneous output power is modulated by adjusting the amplifiers load through a digitally controlled impedance transformation network. The modulator is suited for modulation schemes with moderate peak-to-average power ratio (PAPR), such as π/4 DQPSK. The modulator may also be used for fine gain control in constant envelope modulation schemes. A class E amplifier with digital impedance amplitude modulation is integrated in 90 nm CMOS. It achieves a peak output power of 9 dBm with a PAE of 30% when powered from a 1.2 V supply. The measured EVM is 2.6% for a 6 dBm π/4 DQPSK modulated signal with 2 Mb/s signal rate at 2.4 GHz RF frequency.

IIP2 and HR calibration for an 8-phase harmonic recombination receiver in 28nm

Abstract: Fully integrated CMOS receivers achieve high linearity and low noise due to harmonic recombination but suffer from limited IIP2 and harmonic rejection due to mismatch and inaccuracies. This paper presents an 8-phase harmonic recombination receiver with independent IIP2 HR3 and HR5 calibration techniques. Calibrated >80dBm IIP2 >70dB HR3 and >75dB HR5 are measured.

Signal processing challenges for emerging digital intensive and digitally assisted transceivers with deeply scaled technology (Invited)

Abstract: Mainstream foundries are leaping toward 14nm node and beyond. Although aggressive scaling can substantially improve digital circuit, it is very controversial for analog circuit. However, analog circuit still has to follow the scaling trend because a single chip integration offers key commercial advantages. To optimally achieve the best performance/power/cost tradeoff with deeply scaled technology nodes, there is a clear trend and paradigm shift towards digital intensive and digitally assisted transceivers. Successes of such transceivers have been proven for individual transceiver components and narrow band systems. When targeting emerging communication standards, higher carrier frequencies, further technology scaling and reconfigurable radios, required signal processing design and implementation are orders of magnitudes more challenging but potential gains are promising. Illustrated with a variety of transceivers representing emerging architectures designed for different sub-6GHz and 60GHz communication systems, we will depict key challenges that we experienced in our design and optimization process with 40nm and 28nm technology nodes.

Stochastic a/d converter and method of using stochastic a/d converter

Abstract: PROBLEM TO BE SOLVED: To provide a high accuracy, low power analog-to-digital converter circuit.SOLUTION: The analog-to-digital converter circuit includes: a first converter stage 2 for receiving an analog input signal 1, and generating a first set 3 of conversion bits, a first completion signal 7, and a residual analog output signal 4 representing a difference between the analog input signal and a signal represented by the first set of conversion bits; a second converter stage 5 comprising a clock generation circuit 8 for receiving the first completion signal and generating a clock signal, a plurality of comparators each of which is configured to receive the residual analog output signal and a common reference voltage and which are activated by the clock signal to output a plurality of comparator decisions, and a digital processing stage for receiving the plurality of comparator decisions and generating a second set of conversion bits; and means for generating a digital representation of the analog input signal by combining the first and second sets of conversion bits.