A general model is introduced which is capable of making accurate, quantitative predictions about the phase noise of different types of electrical oscillators by acknowledging the true periodically time-varying nature of all oscillators. This new approach also elucidates several previously unknown design criteria for reducing close-in phase noise by identifying the mechanisms by which intrinsic device noise and external noise sources contribute to the total phase noise. In particular, it explains the details of how 1/f noise in a device upconverts into close-in phase noise and identifies methods to suppress this upconversion. The theory also naturally accommodates cyclostationary noise sources, leading to additional important design insights. The model reduces to previously available phase noise models as special cases. Excellent agreement among theory, simulations, and measurements is observed.

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A general theory of phase noise in electrical oscillators

We present several new simple and accurate expressions for the DC inductance of square, hexagonal, octagonal, and circular spiral inductors. We evaluate the accuracy of our expressions, as well as several previously published inductance expressions, in two ways: by comparison with three-dimensional field solver predictions and by comparison with our own measurements, and also previously published measurements. Our simple expression matches the field solver inductance values typically within around 3%, about an order of magnitude better than the previously published expressions, which have typical errors ground 20% (or more). Comparison with measured values gives similar results: our expressions (and, indeed, the field solver results) match within around 5%, compared to errors of around 20% for the previously published expressions. (We believe most of the additional errors in the comparison to published measured values is due to the variety of experimental conditions under which the inductance was measured.) Our simple expressions are accurate enough for design and optimization of inductors or of circuits incorporating inductors. Indeed, since inductor tolerance is typically on the order of several percent, "more accurate" expressions are not really needed in practice.

/pdf/simple-accurate-expressions-for-planar-spiral-inductances-3guvpwuxsn.pdf

Simple accurate expressions for planar spiral inductances

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Energy efficiency in cellular networks is a growing concern for cellular operators to not only maintain profitability, but also to reduce the overall environment effects. This emerging trend of achieving energy efficiency in cellular networks is motivating the standardization authorities and network operators to continuously explore future technologies in order to bring improvements in the entire network infrastructure. In this article, we present a brief survey of methods to improve the power efficiency of cellular networks, explore some research issues and challenges and suggest some techniques to enable an energy efficient or "green" cellular network. Since base stations consume a maximum portion of the total energy used in a cellular system, we will first provide a comprehensive survey on techniques to obtain energy savings in base stations. Next, we discuss how heterogenous network deployment based on micro, pico and femtocells can be used to achieve this goal. Since cognitive radio and cooperative relaying are undisputed future technologies in this regard, we propose a research vision to make these technologies more energy efficient. Lastly, we explore some broader perspectives in realizing a "green" cellular network technology.

Green Cellular Networks: A Survey, Some Research Issues and Challenges

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Design Of Analog Cmos Integrated Circuits

The work presents the impact of analog front-end effects on the BER performance of MIMO/SDMA-OFDM downlink transmission using minimum mean-squared error transmit processing at the access point The implementation loss due to gain and phase mismatch, analog filtering, clipping and quantization, phase noise, and I/Q mismatch in the front-ends is given

Impact of front-end effects on the performance of downlink OFDM-MIMO transmission

A 0.1-5GHz dual-VCO software-defined sigma delta frequency synthesizer in 45nm digital CMOS

Analog blocks intended for software defined radio have to be targeted to multi-standard operation trying to guarantee at any time a near optimal power-performance trade-off. A novel approach to design a digitally programmable low pass filter (LPF) and variable gain amplifier (VGA) is here defined. These baseband blocks are driven by a Network-on-Chip that is able to set performances like cut-off frequency, selectivity, noise, and gain conveniently adapting the power consumption. The LPF provides a wide frequency tuning range between 0.35MHz and 23.5MHz with an adaptive integrated noise level between 85? Vrms and 163? Vrms and a current consumption that moves from 1.5mA to 18mA. The VGA is made up of 2 cascaded gain stages and provides a gain range from 0dB to 39dB. The prototype was realized in 0.13?m CMOS technology. Measurements results validate the adopted approach.

Flexible baseband Low-Pass Filter and Variable Gain Amplifier for Software Defined Radio Front End

The introduction of several new cellular and connectivity radio standards has attracted the wireless industry to the concept of softwaredefined radio systems, preferably implemented in advanced nanometer CMOS technology. Several novel circuits and architectures have been investigated to cope with the huge design challenges involved, an overview of which will be given in this article. First, two digitally inspired receiver approaches are presented in detail. Discrete-time radio receivers exploit the paradigm that time is better controllable than voltage in modern CMOS, and are implemented using transistors mainly as switches. RF ADCs digitize the signal as close as possible to the antenna, but still require highspeed analog circuits to achieve the required performance. The second part of the article presents a "traditional" direct-conversion architecture, including also a transmitter, where several new circuits and architectures are used to exploit as much as possible the capabilities of a modern digital CMOS technology.

CMOS software-defined radio transceivers: Analog design in digital technology

Since several years research has been carried out on the design of RF circuits in CMOS technologies. Since then, the usability of CMOS for RF design has been demonstrated by several research groups. However, there are still some fundamental problems and limitations which may not be overlooked. The purpose of this work is to present some of those ‘untold pitfalls’ in the design of RF CMOS circuits for fully integrated transceivers for telecommunication applications.

Jan Craninckx

Papers

Impact of front-end effects on the performance of downlink OFDM-MIMO transmission

A 0.1-5GHz dual-VCO software-defined sigma delta frequency synthesizer in 45nm digital CMOS

Flexible baseband Low-Pass Filter and Variable Gain Amplifier for Software Defined Radio Front End

CMOS software-defined radio transceivers: Analog design in digital technology

RF CMOS Design, Some Untold Pitfalls