A general model is introduced which is capable of making accurate, quantitative predictions about the phase noise of different types of electrical oscillators by acknowledging the true periodically time-varying nature of all oscillators. This new approach also elucidates several previously unknown design criteria for reducing close-in phase noise by identifying the mechanisms by which intrinsic device noise and external noise sources contribute to the total phase noise. In particular, it explains the details of how 1/f noise in a device upconverts into close-in phase noise and identifies methods to suppress this upconversion. The theory also naturally accommodates cyclostationary noise sources, leading to additional important design insights. The model reduces to previously available phase noise models as special cases. Excellent agreement among theory, simulations, and measurements is observed.

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A general theory of phase noise in electrical oscillators

We present several new simple and accurate expressions for the DC inductance of square, hexagonal, octagonal, and circular spiral inductors. We evaluate the accuracy of our expressions, as well as several previously published inductance expressions, in two ways: by comparison with three-dimensional field solver predictions and by comparison with our own measurements, and also previously published measurements. Our simple expression matches the field solver inductance values typically within around 3%, about an order of magnitude better than the previously published expressions, which have typical errors ground 20% (or more). Comparison with measured values gives similar results: our expressions (and, indeed, the field solver results) match within around 5%, compared to errors of around 20% for the previously published expressions. (We believe most of the additional errors in the comparison to published measured values is due to the variety of experimental conditions under which the inductance was measured.) Our simple expressions are accurate enough for design and optimization of inductors or of circuits incorporating inductors. Indeed, since inductor tolerance is typically on the order of several percent, "more accurate" expressions are not really needed in practice.

/pdf/simple-accurate-expressions-for-planar-spiral-inductances-3guvpwuxsn.pdf

Simple accurate expressions for planar spiral inductances

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Energy efficiency in cellular networks is a growing concern for cellular operators to not only maintain profitability, but also to reduce the overall environment effects. This emerging trend of achieving energy efficiency in cellular networks is motivating the standardization authorities and network operators to continuously explore future technologies in order to bring improvements in the entire network infrastructure. In this article, we present a brief survey of methods to improve the power efficiency of cellular networks, explore some research issues and challenges and suggest some techniques to enable an energy efficient or "green" cellular network. Since base stations consume a maximum portion of the total energy used in a cellular system, we will first provide a comprehensive survey on techniques to obtain energy savings in base stations. Next, we discuss how heterogenous network deployment based on micro, pico and femtocells can be used to achieve this goal. Since cognitive radio and cooperative relaying are undisputed future technologies in this regard, we propose a research vision to make these technologies more energy efficient. Lastly, we explore some broader perspectives in realizing a "green" cellular network technology.

Green Cellular Networks: A Survey, Some Research Issues and Challenges

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Design Of Analog Cmos Integrated Circuits

A Software-Defined Radio (SDR) analog front-end is presented that provides extensive programmability of LO generator, LNA, mixers, baseband filters and PPA, supporting various wireless communication standards while guaranteeing a near-optimal power/performance trade-off at any time. The circuit is integrated in a 0.13 mum CMOS technology with 1.2 V supply voltage. This transceiver covers the frequency range from 100 MHz up to 6 GHz by exploiting a flexible zero-IF architecture. The receive path achieves a Noise Figure of 4.8 dB at 174 MHz and 6 dB at 2.4 GHz. For a WLAN OFDM 64 QAM output, the transmitter achieves an EVM better than -29 dB for -0.5 dBm output power at 2.4 GHz and -3.1 dBm output power at 4.9 GHz.

A CMOS 100 MHz to 6 GHz software defined radio analog front-end with integrated pre-power amplifier

This paper presents a novel design approach for fully reconfigurable low-voltage delta-sigma analog-digital converters for next-generation wireless applications. This approach guides us to find the power-optimal solution corresponding to the specifications of various wireless standards by exploring single-loop feedback and feedforward topologies with different filter order, number of quantizer bits, and oversampling ratios. Unlike previous multimode designs, this approach provides a better power efficiency. Based on this approach, a system-level design of a digitally programmable delta-sigma modulator for 4G radios is presented.

/pdf/a-design-approach-for-power-optimized-fully-reconfigurable-2uvecwerft.pdf

A Design Approach for Power-Optimized Fully Reconfigurable $\Delta \Sigma$ A/D Converter for 4G Radios

Energy scalable architectures and circuits for SDRs are proposed, for both a reconfigurable RF front-end and a heterogeneous multiprocessor SoC in a baseband platform. A performance/energy manager dynamically exploits the energy scalability and the dynamics in application requirements and propagation environment, realizing low-power operation. For the transmitter, the energy-scalability is translated to an average system-level energy-efficiency improvement of up to 40%.

Architectures and Circuits for Software-Defined Radios: Scaling and Scalability for Low Cost and Low Energy

We present a SAR ADC with comparator-noise-based stochastic residue estimation. The circuit uses a 9 cycle SAR converter to generate a residue, which is then quantized by clocking 16 noisy comparators four times each and digitally calculating the most likely input voltage for the obtained distribution of zeros and ones. The ADC achieves a 60.9 dB SNDR for a near-Nyquist input at 35 MS/s for a purely dynamic power consumption of 12 µW/MHz.

A 60 dB SNDR 35 MS/s SAR ADC With Comparator-Noise-Based Stochastic Residue Estimation

A complementary dynamic single-stage residue amplifier for a pipelined SAR ADC is presented. It re-uses charge typically wasted during the reset phase, and hence improves efficiency by a factor 2× in this block that often dominates the fundamental noise/power trade-off of the ADC. The residue amplifier achieves 90 µVrms input noise for an energy consumption of 1.5 pJ. It is used in a 2-times interleaved 6b coarse/8b fine pipelined SAR ADC. The 40nm CMOS prototype achieves 11 ENOB at 20 MS/s while consuming 165 µW, leading to an energy per conversion step of 4 fJ. It maintains more than 10.8 ENOB at low input frequencies for a clock frequency up to 180 MS/s.

Jan Craninckx

Papers

A CMOS 100 MHz to 6 GHz software defined radio analog front-end with integrated pre-power amplifier

A Design Approach for Power-Optimized Fully Reconfigurable $\Delta \Sigma$ A/D Converter for 4G Radios

Architectures and Circuits for Software-Defined Radios: Scaling and Scalability for Low Cost and Low Energy

A 60 dB SNDR 35 MS/s SAR ADC With Comparator-Noise-Based Stochastic Residue Estimation

A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC