A general model is introduced which is capable of making accurate, quantitative predictions about the phase noise of different types of electrical oscillators by acknowledging the true periodically time-varying nature of all oscillators. This new approach also elucidates several previously unknown design criteria for reducing close-in phase noise by identifying the mechanisms by which intrinsic device noise and external noise sources contribute to the total phase noise. In particular, it explains the details of how 1/f noise in a device upconverts into close-in phase noise and identifies methods to suppress this upconversion. The theory also naturally accommodates cyclostationary noise sources, leading to additional important design insights. The model reduces to previously available phase noise models as special cases. Excellent agreement among theory, simulations, and measurements is observed.

/pdf/a-general-theory-of-phase-noise-in-electrical-oscillators-a928ervz6d.pdf

A general theory of phase noise in electrical oscillators

We present several new simple and accurate expressions for the DC inductance of square, hexagonal, octagonal, and circular spiral inductors. We evaluate the accuracy of our expressions, as well as several previously published inductance expressions, in two ways: by comparison with three-dimensional field solver predictions and by comparison with our own measurements, and also previously published measurements. Our simple expression matches the field solver inductance values typically within around 3%, about an order of magnitude better than the previously published expressions, which have typical errors ground 20% (or more). Comparison with measured values gives similar results: our expressions (and, indeed, the field solver results) match within around 5%, compared to errors of around 20% for the previously published expressions. (We believe most of the additional errors in the comparison to published measured values is due to the variety of experimental conditions under which the inductance was measured.) Our simple expressions are accurate enough for design and optimization of inductors or of circuits incorporating inductors. Indeed, since inductor tolerance is typically on the order of several percent, "more accurate" expressions are not really needed in practice.

/pdf/simple-accurate-expressions-for-planar-spiral-inductances-3guvpwuxsn.pdf

Simple accurate expressions for planar spiral inductances

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Energy efficiency in cellular networks is a growing concern for cellular operators to not only maintain profitability, but also to reduce the overall environment effects. This emerging trend of achieving energy efficiency in cellular networks is motivating the standardization authorities and network operators to continuously explore future technologies in order to bring improvements in the entire network infrastructure. In this article, we present a brief survey of methods to improve the power efficiency of cellular networks, explore some research issues and challenges and suggest some techniques to enable an energy efficient or "green" cellular network. Since base stations consume a maximum portion of the total energy used in a cellular system, we will first provide a comprehensive survey on techniques to obtain energy savings in base stations. Next, we discuss how heterogenous network deployment based on micro, pico and femtocells can be used to achieve this goal. Since cognitive radio and cooperative relaying are undisputed future technologies in this regard, we propose a research vision to make these technologies more energy efficient. Lastly, we explore some broader perspectives in realizing a "green" cellular network technology.

Green Cellular Networks: A Survey, Some Research Issues and Challenges

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Design Of Analog Cmos Integrated Circuits

The present invention relates to a circuit (100) for stabilizing a voltage on a reference node comprising - a digital-to-analog converter (10), DAC, comprising an array of capacitors and arranged for receiving an input voltage ( V in ) via an input node, a voltage ( V ref,DAC ) via a reference node and a DAC code ( code DAC ) via a controller node, said DAC code indicating to which capacitors of the array said voltage ( V ref,DAC ) is to be applied, and for outputting a DAC output voltage ( V out ), - a capacitive network on the reference node comprising a fixed capacitor ( C ref ) arranged to be precharged to an external reference voltage ( V ref ) and a variable capacitor ( C aux ) arranged to be precharged to an external auxiliary voltage ( V aux ) and afterwards to be connected to the reference node, - a measurement block (40) arranged for measuring the actual voltage on the reference node, - a calibration block (50) arranged for being fed with the DAC code and the measured actual voltage and for determining an updated setting of the variable capacitor based on the DAC code and the measured actual voltage.

Circuit for stabilizing a dac reference voltage

In the previous chapter a discrete-time capacitive charge-based transmitter architecture was described. Using switches and capacitors, sizable packets of charge were controllably transferred from the supply to the output stage, which has the important role of increasing the signal output power before driving the subsequent Power Amplifier (PA). To provide the required output swing without degrading the signal’s harmonic performance, in most cases the PPA is supplied with a higher voltage, which increases both power consumption and cost, requiring technology features such as thick-oxide devices and additional voltage regulators. Also to avoid linearity degradation, in many cases the PPA is operated in Class-A mode, which also leads to a significant impact in power consumption. In fact, more than 50 % of the total amount of power consumed in the first charge-based TX was due to the PPA contribution.

Resistive Charge-Based Transmitter

Two different wireless transmitter topologies based on an direct digital-RF amplitude modulator (DAM) are presented: a polar modulator and a direct digital-RF IQ modulator prototype. The DAM consists of 255 basic cells digitally activated by an 8-bit amplitude code to shape a non-constant envelope RF output. The cells are segment-addressed resulting in a very compact 0.007 mm2 chip area in CMOS 90nm. In order to reduce the spectral images due to the discrete-time to continuous-time conversion a 2-fold interpolation has been implemented. The DAM reaches a peak output power of 5 dBm at 2.45 GHz with 23% drain efficiency. Both direct digital modulator architectures fulfill WLAN 802.11g linearity constrains at 2.45 GHz.

Direct digital-RF amplitude modulator in CMOS 90nm

Switched RF Transmitters

This paper describes the architecture and implementation of a Hard Disk Drive (HDD) Embedded Servo Channel chip. The Servo Channel monitors the position of the read-write heads. The heads' positions are then adjusted to seek the required track and to maintain acceptable error rates while reading from or writing to the disk; the chip implements the full Embedded Servo demodulation process. Positional information is extracted from a differential input voltage at 10MHz and can then be read from the chip as four 10-bit words. New head positioning information can be sent to the chip as a 10-bit input word. The chip outputs a head positioning control voltage proportional to the input code. Using the chip, a servo loop can be implemented for head positioning. The device has been fabricated in 1.0 micron CMOS. The die area is 144mil × 142mil (3.7mm × 3.6mm). Power dissipation is 125mW nominal, dropping to 4mW nominal in powerdown mode. Packages are 28-lead SOIC and 32-lead TSOP.

http://ieeexplore.ieee.org/iel5/5468555/5468556/05469319.pdf

Jan Craninckx

Papers

Circuit for stabilizing a dac reference voltage

Resistive Charge-Based Transmitter

Direct digital-RF amplitude modulator in CMOS 90nm

Switched RF Transmitters

A Monolithic All-CMOS Embedded Servo Channel for Hard Disk Drives