Large-scale integration of high-performance electronic components on mechanically flexible substrates may enable new applications in electronics, sensing and energy. Over the past several years, tremendous progress in the printing and transfer of single-crystalline, inorganic micro- and nanostructures on plastic substrates has been achieved through various process schemes. For instance, contact printing of parallel arrays of semiconductor nanowires (NWs) has been explored as a versatile route to enable fabrication of high-performance, bendable transistors and sensors. However, truly macroscale integration of ordered NW circuitry has not yet been demonstrated, with the largest-scale active systems being of the order of 1 cm(2) (refs 11,15). This limitation is in part due to assembly- and processing-related obstacles, although larger-scale integration has been demonstrated for randomly oriented NWs (ref. 16). Driven by this challenge, here we demonstrate macroscale (7×7 cm(2)) integration of parallel NW arrays as the active-matrix backplane of a flexible pressure-sensor array (18×19 pixels). The integrated sensor array effectively functions as an artificial electronic skin, capable of monitoring applied pressure profiles with high spatial resolution. The active-matrix circuitry operates at a low operating voltage of less than 5 V and exhibits superb mechanical robustness and reliability, without performance degradation on bending to small radii of curvature (2.5 mm) for over 2,000 bending cycles. This work presents the largest integration of ordered NW-array active components, and demonstrates a model platform for future integration of nanomaterials for practical applications.

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Nanowire active-matrix circuitry for low-voltage macroscale artificial skin

Networks are a fundamental tool for understanding and modeling complex systems in physics, biology, neuroscience, engineering, and social science. Many networks are known to exhibit rich, lower-order connectivity patterns that can be captured at the level of individual nodes and edges. However, higher-order organization of complex networks—at the level of small network subgraphs—remains largely unknown. Here, we develop a generalized framework for clustering networks on the basis of higher-order connectivity patterns. This framework provides mathematical guarantees on the optimality of obtained clusters and scales to networks with billions of edges. The framework reveals higher-order organization in a number of networks, including information propagation units in neuronal networks and hub structure in transportation networks. Results show that networks exhibit rich higher-order organizational structures that are exposed by clustering based on higher-order connectivity patterns.

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Higher-order organization of complex networks

We demonstrate inkjet printing as a viable method for large-area fabrication of graphene devices. We produce a graphene-based ink by liquid phase exfoliation of graphite in N-methylpyrrolidone. We use it to print thin-film transistors, with mobilities up to ∼95 cm2 V–1 s–1, as well as transparent and conductive patterns, with ∼80% transmittance and ∼30 kΩ/□ sheet resistance. This paves the way to all-printed, flexible, and transparent graphene devices on arbitrary substrates.

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Inkjet-printed graphene electronics.

A method for annealing metal-oxide semiconductor films with deep-ultraviolet light yields thin-film transistors with performance comparable to that of thermally annealed devices, and widens the range of substrates on which such devices can be fabricated. Solution-processable metal-oxide semiconductors are attractive materials for low-cost, flexible electronics, but the need to anneal the deposited materials at relatively high temperatures limits the range of substrates on which such devices can be fabricated. Now Yong-Hoon Kim and colleagues demonstrate that irradiating the solution-cast films with deep ultraviolet light can obviate the need for an annealing step. In this system, photochemical activation serves essentially the same purpose as annealing, and the resulting semiconducting materials have device performance levels comparable to those produced using the high-temperature techniques. Amorphous metal-oxide semiconductors have emerged as potential replacements for organic and silicon materials in thin-film electronics. The high carrier mobility in the amorphous state, and excellent large-area uniformity, have extended their applications to active-matrix electronics, including displays, sensor arrays and X-ray detectors1,2,3,4,5,6,7. Moreover, their solution processability and optical transparency have opened new horizons for low-cost printable and transparent electronics on plastic substrates8,9,10,11,12,13. But metal-oxide formation by the sol–gel route requires an annealing step at relatively high temperature2,14,15,16,17,18,19, which has prevented the incorporation of these materials with the polymer substrates used in high-performance flexible electronics. Here we report a general method for forming high-performance and operationally stable metal-oxide semiconductors at room temperature, by deep-ultraviolet photochemical activation of sol–gel films. Deep-ultraviolet irradiation induces efficient condensation and densification of oxide semiconducting films by photochemical activation at low temperature. This photochemical activation is applicable to numerous metal-oxide semiconductors, and the performance (in terms of transistor mobility and operational stability) of thin-film transistors fabricated by this route compares favourably with that of thin-film transistors based on thermally annealed materials. The field-effect mobilities of the photo-activated metal-oxide semiconductors are as high as 14 and 7 cm2 V−1 s−1 (with an Al2O3 gate insulator) on glass and polymer substrates, respectively; and seven-stage ring oscillators fabricated on polymer substrates operate with an oscillation frequency of more than 340 kHz, corresponding to a propagation delay of less than 210 nanoseconds per stage.

Flexible metal-oxide devices made by room-temperature photochemical activation of sol–gel films

The development of transistors with high gain is essential for applications ranging from switching elements and drivers to transducers for chemical and biological sensing. Organic transistors have become well-established based on their distinct advantages, including ease of fabrication, synthetic freedom for chemical functionalization, and the ability to take on unique form factors. These devices, however, are largely viewed as belonging to the low-end of the performance spectrum. Here we present organic electrochemical transistors with a transconductance in the mS range, outperforming transistors from both traditional and emerging semiconductors. The transconductance of these devices remains fairly constant from DC up to a frequency of the order of 1 kHz, a value determined by the process of ion transport between the electrolyte and the channel. These devices, which continue to work even after being crumpled, are predicted to be highly relevant as transducers in biosensing applications.

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High transconductance organic electrochemical transistors.

We propose a novel Schmitt trigger (ST) based differential 10-transistor SRAM (static random access memory) bitcell suitable for subthreshold operation. The proposed Schmitt trigger based bitcell achieves 1.56 x higher read static noise margin (SNM) ( Vdd = 400 mV) compared to the conventional 6T cell. The robust Schmitt trigger based memory cell exhibits built-in process variation tolerance that gives tight SNM distribution across the process corners. It utilizes differential operation and hence does not require any architectural changes from the present 6T architecture. At iso-area and iso-read-failure probability the proposed memory bitcell operates at a lower (175 mV) Vdd with 18% reduction in leakage and 50% reduction in read/write power compared to the conventional 6T cell. Simulation results show that the proposed memory bitcell retains data at a supply voltage of 150 mV. Functional SRAM with the proposed memory bitcell is demonstrated at 160 mV in 0.13 mum CMOS technology.

A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM

Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates

We analyze Schmitt-Trigger (ST)-based differential-sensing static random access memory (SRAM) bitcells for ultralow-voltage operation. The ST-based SRAM bitcells address the fundamental conflicting design requirement of the read versus write operation of a conventional 6T bitcell. The ST operation gives better read-stability as well as better write-ability compared to the standard 6T bitcell. The proposed ST bitcells incorporate a built-in feedback mechanism, achieving process variation tolerance - a must for future nano-scaled technology nodes. A detailed comparison of different bitcells under iso-area condition shows that the ST-2 bitcell can operate at lower supply voltages. Measurement results on ten test-chips fabricated in 130-nm CMOS technology show that the proposed ST-2 bitcell gives 1.6× higher read static noise margin, 2× higher write-trip-point and 120-mV lower read-Vmin compared to the iso-area 6T bitcell.

Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design

Steep sub-threshold Interband Tunnel FETs (TFETs) are promising candidates for low supply voltage applications with higher switching performance than traditional CMOS. Unlike CMOS, TFETs exhibit uni-directional conduction due to their asymmetric source-drain architecture, and delayed output saturation characteristics. These unconventional characteristics of TFETs pose a challenge for providing good read/write noise margin characteristics in TFET SRAMs. We provide an analysis of 8T and 10T TFET SRAM cells, including Schmitt-Trigger (ST) based cells, to address these shortcomings. By benchmarking a variety of TFET-based SRAM cells, we show the utility of the Schmitt-Trigger feedback mechanism in improving the read/write noise margins, thus enabling ultra low-V CC operation for TFET SRAMs. We also propose a variation model for studying the impact of device-level variation on TFET SRAM cells. We show that the TFET ST SRAM cell has sufficient variation tolerance to operate at low-V CC , and is a very promising cell to achieve a V CC -min of 124mV. The TFET ST cell operating at its V CC -min provides a 1.2x reduction in dynamic energy and 13x reduction in leakage power compared to the best CMOS-based SRAM implementation operating at it's V CC -min, while giving better performance at the same time.

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Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design

A fully integrated switched capacitor voltage regulator (SCVR) with on-die high density MIM capacitor, distributed across a 14 KB register file (RF) load is demonstrated in 22 nm tri-gate CMOS. The multi-conversion-ratio SCVR provides a wide output voltage range of 0.45-1 V from a fixed input voltage of 1.225 V. It achieves 63-84% conversion efficiency and supports a maximum load current density of 0.88 A/mm2. The area overhead of the dedicated SCVR on the load is 3.6%. Measured data is presented on various performance indices in detail. Subsequent learning on tradeoffs between various factors like capacitance characteristics, conversion efficiency and current density are delineated and, correlated with theoretical estimates. Performance of RF array shows comparable results when powered with the SCVR and the external rail. The all-digital, modular design allows efficient spatial distribution across the load and hence robust power delivery. The extremely fast response times in the order of few nanoseconds is targeted to benefit agile power management. This work evinces voltage regulator technology as a standard homogenous CMOS component, which can proliferate DVFS domains for maximum energy and area benefits.

Jaydeep P. Kulkarni

Papers

A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM

Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates

Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design

Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design

A 0.45–1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS