There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

The solid-state transformer (SST) is an interface device between ac distribution grids and dc distribution systems. The SST consists of a cascaded multilevel ac/dc rectifier stage, a dual active bridge (DAB) converter stage with high-frequency transformers to provide a regulated 400-V dc distribution, and an optional dc/ac stage that can be connected to the 400-V dc bus to provide residential 120/240 V $_{\rm ac}$ . However, due to dc-link voltage and power unbalance in the cascaded modules, the unbalanced dc-link voltages and power increase the stress of the semiconductor devices and cause overvoltage or overcurrent issues. This paper proposes a new voltage and power balance control for the cascaded H-Bridge converter-based SST. Based on the single-phase dq model, a novel voltage and the power control strategy is proposed to balance the rectifier capacitor voltages and the real power through parallel DAB modules. Furthermore, the intrinsic power constraints of the cascaded H-Bridge voltage balance control are derived and analyzed. With the proposed control methods, the dc-link voltage and the real power through each module can be balanced. The SST switching model simulation and the prototype experiments are presented to verify the performance of the proposed voltage and power balance controller.

Voltage and Power Balance Control for a Cascaded H-Bridge Converter-Based Solid-State Transformer

This paper presents a comprehensive study on the influences of parasitic elements on the MOSFET switching performance. A circuit-level analytical model that takes MOSFET parasitic capacitances and inductances, circuit stray inductances, and reverse current of the freewheeling diode into consideration is given to evaluate the MOSFET switching characteristics. The equations derived for emulating MOSFET switching transients are assessed graphically, which, compared to results obtained merely from simulation or parametric study, can offer better insight into where the changes in switching performance lie when the parasitic elements are varied. The analysis has been successfully substantiated by the experimental results of a 400 V, 6 A test bench. A discussion on the physical meanings behind these parasitic effect phenomena is included. Knowledge about the effects of parasitic elements on the switching behavior serves as an important basis for the design guidelines of fast switching power converters.

Characterization and Experimental Assessment of the Effects of Parasitic Elements on the MOSFET Switching Performance

Silicon carbide (SiC) switching power devices (MOSFETs, JFETs) of 1200 V rating are now commercially available, and in conjunction with SiC diodes, they offer substantially reduced switching losses relative to silicon (Si) insulated gate bipolar transistors (IGBTs) paired with fast-recovery diodes. Low-voltage industrial variable-speed drives are a key application for 1200 V devices, and there is great interest in the replacement of the Si IGBTs and diodes that presently dominate in this application with SiC-based devices. However, much of the performance benefit of SiC-based devices is due to their increased switching speeds ( di/dt, dv/ dt), which raises the issues of increased electromagnetic interference (EMI) generation and detrimental effects on the reliability of inverter-fed electrical machines. In this paper, the tradeoff between switching losses and the high-frequency spectral amplitude of the device switching waveforms is quantified experimentally for all-Si, Si-SiC, and all-SiC device combinations. While exploiting the full switching-speed capability of SiC-based devices results in significantly increased EMI generation, the all-SiC combination provides a 70% reduction in switching losses relative to all-Si when operated at comparable dv/dt. It is also shown that the loss-EMI tradeoff obtained with the Si-SiC device combination can be significantly improved by driving the IGBT with a modified gate voltage profile.

An Experimental Investigation of the Tradeoff between Switching Losses and EMI Generation With Hard-Switched All-Si, Si-SiC, and All-SiC Device Combinations

Recently, the world's first ever power electronic traction transformer (PETT) for a 15-kV 16.7-Hz railway grid has been newly developed, commissioned, and installed on the test locomotive, where the PETT is presently in use. The design and development of the PETT are described in two parts of this paper. The details related to the 1.2-MVA medium voltage (MV) PETT prototype, including the electrical design of the power circuit, the sizing and characterization of insulated-gate bipolar transistor (IGBT) devices, the design of the medium-frequency transformer, the cooling system design, insulation coordination, and protection, are presented in this part, while the preceding paper deals with the overall system requirements and control system design based on the low-voltage (LV) PETT prototype. The identical control hardware and software from the LV PETT prototype were used for the MV PETT prototype, thus reducing significantly commissioning time. The experimental results obtained during the testing are presented to demonstrate the performance of the developed MV PETT prototype.

Power Electronic Traction Transformer—Medium Voltage Prototype

In this paper, a new strategy for voltage balancing of distinct dc buses in cascaded H-bridge rectifiers is presented. This method ensures that the dc bus capacitor voltages converge to the reference value, even when the loads attached to them are extracting different amounts of power. The proposed method can be used for an arbitrary number of series H-bridges, different voltage levels, and different power levels in unidirectional or bidirectional rectifiers. To reduce the current harmonics and distortion, the input current is programmed to be sinusoidal and in phase with the input voltage; however, it is possible to adjust the input power factor to control both the active and reactive powers. In the proposed approach, both the low frequency (stepped modulation) and high frequency [pulse-width modulation (PWM)] switching methods are utilized to improve the performance of the rectifier. Using theoretical analysis, the acceptable load power limits for a rectifier with N-H-bridge cells are derived. The validity of the proposed method is verified by simulation and experimental results.

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A Modular Strategy for Control and Voltage Balancing of Cascaded H-Bridge Rectifiers

Today, electromagnetic compatibility (EMC) seems to be one of the major constraints of power electronic converters, particularly for variable-speed drives. Unfortunately, it is too often regarded as the last phase of the development of a converter since it represents the last step of its marketing. The estimation of conducted and radiated disturbances by simulation offers a considerable gain from the economic point of view. This paper shows how relatively simple models can be used to forecast EMC, taking into account various control strategies. These models are validated on an experimental setup and can be used during the design of a variable-speed inverter motor association. The objective is to approach by “fast” simulations the conducted emission to consider optimization processes. It is then imperative to take into account the environment of the converter, which implies the modeling of cables, motors, and, naturally, the filters.

/pdf/emi-study-of-a-three-phase-inverter-fed-motor-drives-5b74cufpct.pdf

EMI study of a three phase inverter-fed motor drives

An analytical expression is derived for the power MOSFET turn-off overvoltage, including the influence of PCB interconnects. The entire PCB is modeled by means of the partial element equivalent circuit (PEEC) method. The PCB model associated with a simple MOSFET model permits computation of maximum overvoltage with good precision. This expression can be used to design PCBs and choose a type of MOSFET respecting MOSFET maximum voltage ratings. The analytical expression has been verified by breadboard experiments.

MOSFET switching behaviour under influence of PCB stray inductance

The reduced switching times of silicon carbide (SiC) components compared to Si components in similar conditions are a great advantage from the point of view of efficiency, but, due to the high dv/dt and di/dt, conducted electromagnetic emissions are increased. Therefore, the availability of a method which can predict these emissions is increasingly necessary. To the best of the authors' knowledge, a model that can predict differential mode as well as common mode for a converter including sic devices has not yet been published. the novelty of the work presented here is the integration of different modeling approaches to form a circuit model of a SiC-based buck dc-dc converter working in frequency range from 40 Hz to 30 MHz. A modeling approach of the passive parts of the converter is presented. Then, the model obtained is used in simulations to predict the drain-to-source voltage and the drain current for the JFET. Conducted emissions received by the line impedance stabilization network are also computed. Simulation results are compared to measurements for different duty cycles and different gate resistors in the time and frequency domains. A good agreement is obtained. In the frequency domain, in all cases, differences are less than 5 dBμV up to 30 MHz excepted in the JFET source current.

Modeling of a Buck Converter With a SiC JFET to Predict EMC Conducted Emissions

Among the various solutions for the series association of high power IGBTs, the active clamping circuit insures both protection and voltage balancing, within good reliability and compactness. Therefore, this structure has been chosen to be integrated closed to the IGBTs. The design of this circuit leads to the resolution of a compromise between a good balancing and limited additional losses. The aim of this paper is to optimise this circuit, in order to reduce the losses, in the IGBTs as well as in the active clamping circuit. This design has been validated in a 3 kV 400 A test bench, using three 1.7 kV components in series.

Jean-Luc Schanen

Papers

A Modular Strategy for Control and Voltage Balancing of Cascaded H-Bridge Rectifiers

EMI study of a three phase inverter-fed motor drives

MOSFET switching behaviour under influence of PCB stray inductance

Modeling of a Buck Converter With a SiC JFET to Predict EMC Conducted Emissions

Optimisation and integration of an active clamping circuit for IGBT series association