This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specific to each attempt is presented. A new device structure called the dual-material gate (DMG) SOI MOSFET is discussed and its efficacy in suppressing SCEs such as drain-induced barrier lowering (DIBL), channel length modulation and hot-carrier effects, all of which affect the reliability of ultra-small geometry MOSFETs, is assessed.

https://web.iitd.ac.in/~mamidala/HTMLobj-161/March04.pdf

Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review

In this paper, we propose the application of a dual material gate (DMG) in a tunnel field-effect transistor (TFET) to simultaneously optimize the on-current, the off-current, and the threshold voltage and also improve the average subthreshold slope, the nature of the output characteristics, and immunity against the drain-induced barrier lowering effects. We demonstrate that, if appropriate work functions are chosen for the gate materials on the source side and the drain side, the TFET shows a significantly improved performance. We apply the technique of DMG in a strained double-gate TFET with a high-k gate dielectric to show an overall improvement in the characteristics of the device, along with achieving a good on-current and an excellent average subthreshold slope. The results show that the DMG technique can be applied to TFETs with different channel materials, channel lengths, gate-oxide materials, gate-oxide thicknesses, and power supply levels to achieve significant gains in the overall device characteristics.

Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field-Effect Transistor

A two-dimensional (2-D) analytical model for the surface potential variation along the channel in fully depleted dual-material gate silicon-on-insulator MOSFETs is developed to investigate the short-channel effects (SCEs). Our model includes the effects of the source/drain and body doping concentrations, the lengths of the gate metals and their work functions, applied drain and substrate biases, the thickness of the gate and buried oxide and also the silicon thin film. We demonstrate that the surface potential in the channel region exhibits a step function that ensures the screening of the drain potential variation by the gate near the drain resulting in suppressed SCEs like the hot-carrier effect and drain-induced barrier-lowering (DIBL). The model is extended to find an expression for the threshold voltage in the submicrometer regime, which predicts a desirable "rollup" in the threshold voltage with decreasing channel lengths. The accuracy of the results obtained using our analytical model is verified using 2-D numerical simulations.

https://web.iitd.ac.in/~mamidala/HTMLobj-160/april04.pdf

Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs

In this paper, we present the unique features exhibited by a modified asymmetrical double-gate (DG) silicon-on-insulator (SOI) MOSFET. The proposed structure is similar to that of the asymmetrical DG SOI MOSFET with the exception that the front gate consists of two materials. The resulting modified structure, i.e., a dual-material double-gate (DMDG) SOI MOSFET, exhibits significantly reduced short-channel effects (SCEs) when compared with the DG SOI MOSFET. SCEs in this structure have been studied by developing an analytical model. The model includes the calculation of the surface potential, electric field, threshold voltage, and drain-induced barrier lowering. A model for the drain current, transconductance, drain conductance, and voltage gain is also discussed. It is seen that SCEs in this structure are suppressed because of the perceivable step in the surface-potential profile, which screens the drain potential. We further demonstrate that the proposed DMDG structure provides a simultaneous increase in the transconductance and a decrease in the drain conductance when compared with the DG structure. The results predicted by the model are compared with those obtained by two-dimensional simulation to verify the accuracy of the proposed analytical model.

https://web.iitd.ac.in/~mamidala/HTMLobj-248/March05NANO.pdf

A new dual-material double-gate (DMDG) nanoscale SOI MOSFET-two-dimensional analytical modeling and simulation

In this paper, we present the unique features exhibited by modified asymmetrical Double Gate (DG) silicon on insulator (SOI) MOSFET. The proposed structure is similar to that of the asymmetrical DG SOI MOSFET with the exception that the front gate consists of two materials. The resulting modified structure, Dual Material Double Gate (DMDG) SOI MOSFET, exhibits significantly reduced short channel effects when compared with the DG SOI MOSFET. Short channel effects in this structure have been studied by developing an analytical model. The model includes the calculation of the surface potential, electric field, threshold voltage and drain induced barrier lowering. A model for the drain current, transconductance, drain conductance and voltage gain is also discussed. It is seen that short channel effects in this structure are suppressed because of the perceivable step in the surface potential profile, which screens the drain potential. We further demonstrate that the proposed DMDG structure provides a simultaneous increase in the transconductance and a decrease in the drain conductance when compared with the DG structure. The results predicted by the model are compared with those obtained by two-dimensional simulation to verify the accuracy of the proposed analytical model.

A New Dual-Material Double-Gate (DMDG) Nanoscale SOI MOSFET - Two-dimensional Analytical Modeling and Simulation

A generic new type of field effect transistor (FET), the dual material gate (DMG) FET, is proposed and demonstrated. The gate of the DMGFET consists of two laterally contacting materials with different work functions. This novel gate structure takes advantage of material work function difference in such a way that the threshold voltage near the source is more positive than that near the drain (for n-channel FET, the opposite for p-channel FET), resulting in a more rapid acceleration of charge carriers in the channel and a screening effect to suppress short-channel effects. Using the heterostructure FET as a vehicle, the principle, computer simulation results, design guidelines, processing, and characterization of the DMGFET are discussed in detail.

Dual-material gate (DMG) field effect transistor

The quaternary (Al/sub x/Ga/sub 1-x/)/sub 0.5/In/sub 0.5/P (0/spl les//spl times//spl les/1) compounds on GaAs substrates are important materials used as a Schottky layer in microwave devices. In this report, we systematically investigated the electrical properties of quaternary (Al/sub x/Ga/sub 1-x/)/sub 0.5/In/sub 0.5/P materials and concluded that the best composition for improving the device performance is by substituting 30% (x=0.3) of Ga atoms for Al atoms in GaInP material. The Schottky barrier heights (/spl phi/B) of (Al/sub x/Ga/sub 1-x/)/sub 0.5/In/sub 0.5/P layers were 0.85/spl sim/1.00 eV. We successfully realized the (Al/sub x/Ga/sub 1-x/)/sub 0.5/In/sub 0.5/P/In/sub 0.15/Ga/sub 0.85/As (x=0, 0.3, 1.0) doped-channel FETs (DCFETs) and demonstrated excellent dc, microwave, and power characteristics.

(Al/sub x/Ga/sub 1-x/)/sub 0.5/In/sub 0.5/P/In/sub 0.15/Ga/sub 0.85/As (x=0, 0. 3, 1. 0) heterostructure doped-channel FETs for microwave power applications

BCl/sub 3/+CHF/sub 3/ gas mixtures for the reactive ion etching process were applied to the gate-recess for fabricating (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P quaternary heterostructure double doped-channel FET's (D-DCFET), where a high uniformity of Vth was achieved. With the merits of this wide bandgap (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P layer, microwave power performance of this heterostructure D-DCFET demonstrates a compatible performance for devices fabricated on AlGaAs/InGaAs heterostructures.

RIE gate-recessed (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P/InGaAs double doped-channel FETs using CHF 3 +BCl 3 mixing plasma

The quaternary (Al Ga ) In P compounds on GaAs substrates are important materials used as a Schottky layer in microwave devices. In this report, we systematically investigated the electrical properties of quaternary (Al Ga ) In P materials and concluded that the best com- position for improving the device performance is by substituting 30% of Ga atoms for Al atoms in GaInP material. The Schottky barrier heights of (Al Ga ) In P layers were eV. We successfully realized the Therefore, in this study, we first systematically grew and characterized various (Al Ga ) In P qua- ternary compounds. The Schottky barrier height of these quaternary compounds were investigated. Secondly, in order to obtain a high-process uniformity, the reactive ion etching (RIE) technology was applied to characterize the etching properties of the AlGaInP materials. Finally, we used this high quality (Al Ga ) In P quaternary material system as a Schottky layer, combining a super transport In Ga As doped channel, to realize the (Al Ga ) In P/In Ga As double doped-channel FETs (DCFETs), and evaluated their dc and microwave power performances. DCFETs, based on our previous studies, have achieved excellent device linearity, current density, and breakdown voltage, as compared with PHEMTs, which are the important factors for device power applications (4).

http://ieeexplore.ieee.org/iel5/16/21013/00974726.pdf

(Al Ga ) In P/In Ga As Heterostructure Doped-Channel FETs for Microwave Power Applications

BCl CHF gas mixture for reactive ion etching process was used to the gate-recess of fabricat- ing (Al Ga ) In P quaternary heterostructure double doped-channel FET's (D-DCFET), where a high uniformity of was achieved. With the merits of this wide bandgap (Al Ga ) In P layer, microwave power performance of this heterostructure D-DCFET demonstrates a compatible perfor- mance for devices fabricated on AlGaAs/InGaAs heterostructures. Index Terms—AlGaInP/InGaAs, heterostructure FETs, reac- tive-ion-etching.

http://ieeexplore.ieee.org/iel5/55/19783/00915602.pdf

Jenn-Ming Kuo

Papers

Dual-material gate (DMG) field effect transistor

(Al/sub x/Ga/sub 1-x/)/sub 0.5/In/sub 0.5/P/In/sub 0.15/Ga/sub 0.85/As (x=0, 0. 3, 1. 0) heterostructure doped-channel FETs for microwave power applications

RIE gate-recessed (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P/InGaAs double doped-channel FETs using CHF 3 +BCl 3 mixing plasma

(Al Ga ) In P/In Ga As Heterostructure Doped-Channel FETs for Microwave Power Applications

RIE Gate-Recessed (Al Ga ) In P/InGaAs Double Doped-Channel FETs Using CHF BCl Mixing Plasma