Jeong Dong Choe

TL;DR: In this paper, the authors demonstrate a double FinFET on bulk Si wafer, named multi-channel field effect transistor (McFET), for the high performance 80nm 144M SRAM.

TL;DR: In this paper, the operational six-transistor SRAM cell characteristic was demonstrated using body-tied triple-gate MOSFETs, and a cell size of 0.79 /spl mu/m/sup 2/ was achieved with 90-nm node technology, using four levels of W and Al interconnects.

TL;DR: In this paper, a partially insulated field effect transistors (PiFETs) were fabricated by using Si-SiGe epitaxial growth and selective SiGe etch process.

TL;DR: In this article, a MOS transistor with a through plug penetrates the buried insulating layer and electrically connects the body region with the lower semiconductor substrate, the through plug positioned closer to one of the source/drain regions than the other source/drain region.

TL;DR: By manipulating the charge profile through the inverted sidewall patterning on the channel, stable 2-bit operation in siliconoxide-nitride-oxide-silicon (SONOS) Flash memory with sub-90-nm gate length can be achieved as mentioned in this paper.