We have demonstrated a 70-nm n-channel tunneling field-effect transistor (TFET) which has a subthreshold swing (SS) of 52.8 mV/dec at room temperature. It is the first experimental result that shows a sub-60-mV/dec SS in the silicon-based TFETs. Based on simulation results, the gate oxide and silicon-on-insulator layer thicknesses were scaled down to 2 and 70 nm, respectively. However, the ON/ OFF current ratio of the TFET was still lower than that of the MOSFET. In order to increase the on current further, the following approaches can be considered: reduction of effective gate oxide thickness, increase in the steepness of the gradient of the source to channel doping profile, and utilization of a lower bandgap channel material

Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec

Steep subthreshold swing transistors based on interband tunneling are examined toward extending the performance of electronics systems. In particular, this review introduces and summarizes progress in the development of the tunnel field-effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges. The promise of the TFET is in its ability to provide higher drive current than the MOSFET as supply voltages approach 0.1 V.

/pdf/low-voltage-tunnel-transistors-for-beyond-cmos-logic-3w5c8knrc5.pdf

Low-Voltage Tunnel Transistors for Beyond CMOS Logic

Applied Numerical Analysis. By C.F. Gerald. Pp. xii, 340. £3·60. 1970. (Addison-Wesley.)

Semiconductors for organic transistors

2.2. Interface Trapping Effects 211 3. High-k Dielectric Materials for OFETs 212 3.1. Inorganic Dielectrics 212 3.1.1. Aluminum Oxide 213 3.1.2. Tantalum Oxide 215 3.1.3. Titanium Dioxide 216 3.1.4. Hafnium Dioxide 217 3.1.5. Zirconium Dioxide 218 3.1.6. Cerium Dioxide 218 3.2. Organic Dielectrics 218 3.2.1. Polymer Dielectrics 218 3.2.2. Self-Assembled Monoand Multilayers 225 3.3. Hybrid Dielectrics 227 3.3.1. Polymeric-Nanoparticle Composites 227 3.3.2. Inorganic-Organic Bilayers 232 3.3.3. Hybrid Solid Polymer Electrolytes 235 4. Summary 235 5. Acknowledgments 236 6. References 236

High-k organic, inorganic, and hybrid dielectrics for low-voltage organic field-effect transistors.

In this paper, a 3-D NAND Flash memory array having multiple single-crystal Si nanowires is investigated. Device structure and fabrication process are described including the electrical isolation of stacked nanowires. Numerical simulation results focused on NAND Flash memory operation are delivered. Devices and array with stacked bit lines are fabricated, and memory characteristics such as program/erase select gate operation are measured. Array scheme is also discussed for the high-density bit-cost scalable 3-D stacked bit-line NAND Flash memory application.

Single-Crystalline Si STacked ARray (STAR) NAND Flash Memory

The origin of the hysteresis phenomenon in bottom-contact pentacene organic thin-film transistors (OTFTs) with cross-linked poly(vinyl alcohol) (PVA) insulator is studied. From electrical measurements with various sweep ranges and two different sweep directions, the hysteresis effect is presumed to be caused by the electrons or holes that could be injected from the gate and trapped in the PVA bulk, rather than by the polarization or internally existing mobile ions. The assumption is confirmed by the clear reduction of hysteresis in OTFTs with a blocking oxide layer between gate and PVA insulator.

Hysteresis mechanism and reduction method in the bottom-contact pentacene thin-film transistors with cross-linked poly(vinyl alcohol) gate insulator

We propose a surrounding gate MOSFET with vertical channel (SGVC cell) as a 1T DRAM cell. To confirm the memory operation of the SGVC cell, we simulated its memory effect and fabricated the highly scalable SGVC cell. According to simulation and measurement results, the SGVC cell can operate as a 1T DRAM having a sufficiently large sensing margin. Also, due to its vertical channel structure and common source architecture, it can readily be made into a 4F2 cell array

A New Capacitorless 1T DRAM Cell: Surrounding Gate MOSFET With Vertical Channel (SGVC Cell)

70-nm I-MOS devices have been integrated with 70-nm TFETs for the first time by adopting a novel process method The integration of the I-MOS device with the TFET is meaningful in that it compensates for weak points of each device and implements both high-performance and low-power functionality on the same substrate Additionally, by using SOI substrate and modifying mask layout, ON/OFF current ratio of the I-MOS device is increased dramatically by a factor of more than 1000 compared with our previous works Finally, we have investigated the applicability of the I-MOS device to inverter and 6T-SRAM cell by measurement and mixed-mode simulation When applied to 6T-SRAM cell, CI-MOS case shows 226 % improvement in SNM without much penalty in cell area

Jong Duk Lee

Papers

Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec

Single-Crystalline Si STacked ARray (STAR) NAND Flash Memory

Hysteresis mechanism and reduction method in the bottom-contact pentacene thin-film transistors with cross-linked poly(vinyl alcohol) gate insulator

A New Capacitorless 1T DRAM Cell: Surrounding Gate MOSFET With Vertical Channel (SGVC Cell)

70-nm impact-ionization metal-oxide-semiconductor (I-MOS) devices integrated with tunneling field-effect transistors (TFETs)