An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

In fabricating a thin film transistor, an active layer comprising a silicon semiconductor is formed on a substrate having an insulating surface Hydrogen is introduced into The active layer A thin film comprising SiO x N y is formed to cover the active layer and then a gate insulating film comprising a silicon oxide film formed on the thin film comprising SiO x N y  Also, a thin film comprising SiO x N y is formed under the active layer The active layer includes a metal element at a concentration of 1×10 15 to 1×10 19 cm −3 and hydrogen at a concentration of 2×10 19 to 5×10 21 cm −3 

Semiconductor device and method for forming the same

This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Considerations for Ultimate CMOS Scaling

Progress in the development of tunnel field-effect transistors (TFETs) is reviewed by comparing experimental results and theoretical predictions against 16-nm FinFET CMOS technology. Experiments lag the projections, but sub-threshold swings less than 60 mV/decade are now reported in 14 TFETs. The lowest measured sub-threshold swings approaches 20 mV/decade, however, the measurements at these lowest values are not based on many points. The highest current at which sub-threshold swing below 60 mV/decade is observed is in the range 1–10 nA/ \({{\mu }}\) m. A common approach to TFET characterization is proposed to facilitate future comparisons.

Tunnel Field-Effect Transistors: State-of-the-Art

A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.

System and methods for converting planar design to FinFET design

A method includes forming a dielectric layer over a portion of an SRAM cell. The SRAM cell includes a first pull-up transistor and a second pull-up transistor, a first pull-down transistor and a second pull-down transistor forming cross-latched inverters with the first pull-up transistor and the second pull-up transistor, and a first pass-gate transistor and a second pass-gate transistor connected to drains of the first pull-up transistor and the first pull-down transistor and drains of the second pull-up transistor and the second pull-down transistor, respectively. A first mask layer is formed over the dielectric layer and patterned. A second mask layer is formed over the dielectric layer and patterned. The dielectric layer is etched using the first mask layer and the second mask layer in combination as an etching mask, wherein a contact opening is formed in the dielectric layer. A contact plug is formed in the contact opening.

Contact plugs in SRAM cells and the method of forming the same

A process for forming a tungsten plug structure, in a narrow diameter contact hole, has been developed. The process features the use of a composite layer, comprised on an underlying titanium layer, and an overlying, first titanium nitride barrier layer, on the walls, and at the bottom, of the narrow diameter contact hole. After an RTA procedure, used to create a titanium silicide layer, at the bottom of the narrow diameter contact hole, a second titanium nitride layer is deposited, to fill possible defects in the underlying first titanium nitride, that may have been created during the RTA procedure. The tungsten plug structure is then formed, embedded by dual titanium nitride barrier layers.

Two step barrier process

A memory structure that reduces soft-errors for us in CMOS devices is provided. The memory cell layout utilizes transistors oriented such that the source-to-drain axis is parallel a shorted side of the memory cell. The dimensions of the memory cell are such that it has a longer side and a shorter side, wherein the longer side is preferably about twice as long as the shorter side. Such an arrangement uses a shorter well path to reduce the resistance between transistors and the well strap. The shorter well strap reduces the voltage during operation and soft errors.

Memory cell structure

FinFET technology has become a mainstream technology solution for post-20nm CMOS technology [1], since it has superior short-channel effects, better sub-threshold slope and reduced random dopant fluctuation. Therefore, it is expected to achieve better performance with lower SRAM VDDMIN. However, the quantized sizing of the channel width and length has drawbacks for conventional 6T-SRAM bitcell scaling. To minimize the bitcell area of the high-density SRAM bitcell, the number of fins (setting the channel width, W) of the pull-up PMOS (PU), passgate NMOS (PG) and pull-down NMOS (PD) transistors must be selected as 1:1:1. Since PU, PG, and PD have the same channel length (L), the ratio in geometry between the PU transistor and the PG transistor is equal to one. With the process variations, the strength of PU transistor can be much stronger than the PG transistor. A stronger PU transistor increases read stability of the SRAM bitcell but it degrades the write margin significantly and results in worse write-VDDMIN issue. Figure 13.5.1(a) shows a contention condition between PU and PG transistors of a 6T-SRAM bitcell for the write operation. During the write operation, the PU transistor impedes the ability of the PG transistor to pull the storage node (S) from VDD to ground. The bitcell may suffer a write failure at the stronger PU with weaker PG condition caused by the device variations. Two techniques have been proposed to improve the high density SRAM bitcell write VDDMIN: 1) negative bit-line voltage (NBL) to increase the strength of PG transistor and 2) lower cell VDD (LCV) to weaken PU transistor strength [1-5]. Compared to the conventional techniques, this work develops a suppressed-coupling-signal negative bitline (SCS-NBL) scheme and a write-recovery-enhancement lower-cell-VDD (WRE-LCV) scheme for write assist without the concern of reliability at higher VDD operating region. A comparison of the effectiveness of the two design techniques is also performed. Figure 13.5.1(b) shows the layout view of the high-density 6T-SRAM bit-cell with 0.07μm2 area in a 16nm high-k metal-gate FinFET technology. To minimize area, we set the geometric ratio of PU, PG, and PD transistors all equal to one. With the two developed write-assist circuits, the overall VDDMIN improvement can be over 300mV in a 128Mb SRAM test-chip.

13.5 A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-V MIN applications

For the first time, we present a state-of-the-art energy-efficient 16nm technology integrated with FinFET transistors, 0.07um2 high density (HD) SRAM, Cu/low-k interconnect and high density MiM for mobile SoC and computing applications. This technology provides 2X logic density and >35% speed gain or >55% power reduction over our 28nm HK/MG planar technology. To our knowledge, this is the smallest fully functional 128Mb HD FinFET SRAM (with single fin) test-chip demonstrated with low Vccmin for 16nm node. Low leakage (SVt) FinFET transistors achieve excellent short channel control with DIBL of <;30 mV/V and superior Idsat of 520/525 uA/um at 0.75V and Ioff of 30 pA/um for NMOS and PMOS, respectively.

Jhon-Jhy Liaw

Papers

Contact plugs in SRAM cells and the method of forming the same

Two step barrier process

Memory cell structure

13.5 A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-V MIN applications

A 16nm FinFET CMOS technology for mobile SoC and computing applications