J
J.H. Chen
Researcher at TSMC
Publications - 8
Citations - 525
J.H. Chen is an academic researcher from TSMC. The author has contributed to research in topics: CMOS & Logic gate. The author has an hindex of 6, co-authored 8 publications receiving 477 citations.
Papers
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Proceedings ArticleDOI
A 16nm FinFET CMOS technology for mobile SoC and computing applications
Shien-Yang Wu,Lin Chih-Yung,M.C. Chiang,Jhon-Jhy Liaw,Joy Cheng,S.H. Yang,Liang Min-Chang,T. Miyashita,C.H. Tsai,B. C. Hsu,H. Y. Chen,T. Yamamoto,S.Y. Chang,Vincent S. Chang,C.H. Chang,J.H. Chen,Hou-Yu Chen,Kai-Yuan Ting,Y.K. Wu,K.H. Pan,R.F. Tsui,C.H. Yao,P. R. Chang,H. M. Lien,Tze-Liang Lee,H. M. Lee,W. Chang,T. Chang,R. Chen,M. Yeh,Chun-Kuang Chen,Yuan-Hung Chiu,Y. H. Chen,H. C. Huang,Y. C. Lu,Chang Chih-Yang,Ming-Huan Tsai,C. C. Liu,Kuei-Shun Chen,C. C. Kuo,H. T. Lin,S. M. Jang,Y. Ku +42 more
TL;DR: This is the smallest fully functional 128Mb HD FinFET SRAM (with single fin) test-chip demonstrated with low Vccmin for 16nm node and provides 2X logic density and 2X speed gain over 28nm HK/MG planar technology.
Proceedings ArticleDOI
High performance 22/20nm FinFET CMOS devices with advanced high-K/metal gate scheme
C. C. Wu,Derek Lin,A. Keshavarzi,C.H. Huang,C.T. Chan,Tseng Chien-Hsien,Chun Chen,Hsieh Ching-Hua,King-Yuen Wong,M.L. Cheng,T.H. Li,Y.C. Lin,L.Y. Yang,C. P. Lin,Chuan-Ping Hou,H. C. Lin,J.L. Yang,K. F. Yu,Ming-Jer Chen,T.H. Hsieh,Y. C. Peng,Chou Chun-Hao,Lee Chia-Fu,Chien-Chao Huang,Chih-Yuan Lu,F.K. Yang,Huan-Neng Chen,L.W. Weng,P.C. Yen,Wang Shiang-Bau,Stock Chang,S.W. Chuang,T.C. Gan,Tzong-Lin Wu,Tsung-Lin Lee,W.S. Huang,Yi-Chun Huang,Y.W. Tseng,C.M. Wu,Eric Ou-Yang,K.Y. Hsu,L.T. Lin,S.B. Wang,Tsz-Mei Kwok,Chien-Chang Su,C.H. Tsai,Ming-Jie Huang,Huan-Just Lin,A.S. Chang,S.H. Liao,Li-Shiun Chen,J.H. Chen,P.S. Lim,X.F. Yu,S.Y. Ku,Yung-Huei Lee,P.C. Hsieh,Po-Kang Wang,Yuan-Hung Chiu,S.S. Lin,Hun-Jan Tao,M. Cao,Yuh-Jier Mii +62 more
TL;DR: In this article, a 22/20nm CMOS bulk FinFET with dual workfunction (WF) with an advanced High-K/Metal gate (HK/MG) stack is deployed in an integration-friendly CMOS process flow.
Proceedings ArticleDOI
A 7nm CMOS platform technology featuring 4 th generation FinFET transistors with a 0.027um 2 high density 6-T SRAM cell for mobile SoC applications
Shien-Yang Wu,Lin Chih-Yung,M.C. Chiang,Jhon-Jhy Liaw,Joy Cheng,S.H. Yang,C.H. Tsai,P N Chen,T. Miyashita,C.H. Chang,Vincent S. Chang,K.H. Pan,J.H. Chen,Y S Mor,K T Lai,C S Liang,Hou-Yu Chen,S.Y. Chang,Chia-Pin Lin,C. H. Hsieh,R.F. Tsui,C.H. Yao,Chun-Kuang Chen,R. Chen,C. H. Lee,Hon-Jarn Lin,Chang Chih-Yang,Kuang-Hsin Chen,Ming-Huan Tsai,Kuei-Shun Chen,Y. Ku,S. M. Jang +31 more
TL;DR: In this paper, the authors presented a leading edge 7nm CMOS platform technology for mobile SoC applications, which provides >3.3X routed gate density and 35%∼40% speed gain or >65% power reduction over 16nm FinFET technology.
A 7nm CMOS platform technology featuring 4 th generation FinFET transistors with a 0.027um 2 high density 6-T SRAM cell for mobile SoC applications
Wu Shien-Yang,Lin Chih-Yung,M.C. Chiang,J J Liaw,Joy Cheng,S.H. Yang,C.H. Tsai,P N Chen,T Miyashita,C.H. Chang,V S Chang,K.H. Pan,J.H. Chen,Y S Mor,K T Lai,C S Liang,Hou-Yu Chen,S.Y. Chang,Chia-Pin Lin,C H Hsieh,R.F. Tsui,C.H. Yao,C C Chen,R. Chen,C. H. Lee,Hua-Tai Lin,Chang Chih-Yang,Kuang-Hsin Chen,M H Tsai,K S Chen,Y. Ku,S. M. Jang +31 more
TL;DR: For the first time, a leading edge 7nm CMOS platform technology for mobile SoC applications is presented and a fully functional 256Mb SRAM test-chip with the smallest high density SRAM cell of 0.027um2 is demonstrated down to 0.5V.
Proceedings ArticleDOI
An enhanced 16nm CMOS technology featuring 2 nd generation FinFET transistors and advanced Cu/low-k interconnect for low power and high performance applications
Shien-Yang Wu,Lin Chih-Yung,M.C. Chiang,Jhon-Jhy Liaw,Joy Cheng,S.H. Yang,S.Z. Chang,Liang Min-Chang,T. Miyashita,C.H. Tsai,C.H. Chang,Vincent S. Chang,Y.K. Wu,J.H. Chen,Hou-Yu Chen,S.Y. Chang,K.H. Pan,R.F. Tsui,C.H. Yao,Kai-Yuan Ting,T. Yamamoto,H.T. Huang,Tze-Liang Lee,C. H. Lee,W. Chang,H. M. Lee,Chun-Kuang Chen,T. Chang,R. Chen,Yuan-Hung Chiu,Ming-Huan Tsai,S. M. Jang,Kuei-Shun Chen,Y. Ku +33 more
TL;DR: In this paper, an enhanced 16nm CMOS technology featuring the second generation FinFET transistors and advanced Cu/low-k interconnect is presented to provide additional 15% speed boost or 30% power reduction.