GaN based high electron mobility transistors (HEMTs) have demonstrated extraordinary features in the applications of high power and high frequency devices. In this paper, we review recent progress in AlGaN/GaN HEMTs, including the following sections. First, challenges in device fabrication and optimizations will be discussed. Then, the latest progress in device fabrication technologies will be presented. Finally, some promising device structures from simulation studies will be discussed.

https://www.mdpi.com/2079-9292/7/12/377/pdf

A Comprehensive Review of Recent Progress on GaN High Electron Mobility Transistors: Devices, Fabrication and Reliability

We investigate the performance of hysteresis-free short-channel negative-capacitance FETs (NCFETs) by combining quantum-mechanical calculations with the Landau–Khalatnikov equation. When the subthreshold swing (SS) becomes smaller than 60 mV/dec, a negative value of drain-induced barrier lowering is obtained. This behavior, drain-induced barrier rising (DIBR), causes negative differential resistance in the output characteristics of the NCFETs. We also examine the performance of an inverter composed of hysteresis-free NCFETs to assess the effects of DIBR at the circuit level. Contrary to our expectation, although hysteresis-free NCFETs are used, hysteresis behavior is observed in the transfer properties of the inverter. Furthermore, it is expected that the NCFET inverter with hysteresis behavior can be used as a Schmitt trigger inverter.

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Analysis of Drain-Induced Barrier Rising in Short-Channel Negative-Capacitance FETs and Its Applications

We make a 2-D analysis of breakdown characteristics of field-plate AlGaN/GaN HEMTs with a high- ${k}$ passivation layer, and the results are compared with those having a normal SiN passivation layer. As a result, it is found that the breakdown voltage is enhanced particularly in the cases with relatively short field plates because the reduction in the electric field at the drain edge of gate effectively improves the breakdown voltage in the case with the high- ${k}$ passivation layer. In the case with the moderate-length field plate, the enhancement of breakdown voltage due to the high- ${k}$ passivation layer occurs because the electric field profiles between the field-plate edge and the drain become more uniform. It is also studied how the breakdown voltage depends on a deep-acceptor density in the Fe-doped semi-insulating buffer layer when a high- ${k}$ passivation layer is used. It is shown that the breakdown voltage increases with increasing the relative permittivity of the passivation layer $\varepsilon _{\text{r}}$ and with increasing the deep-acceptor density NDA. When $\varepsilon _{\text{r}} = 60$ and $N_{\mathrm {DA}} = 2$ – $3 \times 10^{17}$ cm−3 at the gate length of $0.3~\mu \text{m}$ , the breakdown voltage becomes about 500 V at a gate-to-drain distance of $1.5~\mu \text{m}$ , which corresponds to an average electric field of about 3.3 MV/cm between the gate and the drain.

/pdf/enhancement-of-breakdown-voltage-in-algan-gan-hemts-field-3v836at2dn.pdf

Enhancement of Breakdown Voltage in AlGaN/GaN HEMTs: Field Plate Plus High- ${k}$ Passivation Layer and High Acceptor Density in Buffer Layer

A gate engineered InGaN dopingless tunnel FET (DL-TFET) using the charge plasma concept is proposed and investigated by silvaco Atlas simulation. In0.75Ga0.25N is a direct gap semiconductor, and the effective tunneling mass of electron and hole is smaller than that of silicon, which induces that the drain current and average subthreshold swing (SSavg) of InGaN DL-TFET improve $\text {1.3}\times \text {10}^{\text {2}}$ times and 51.1% than that of Si DL-TFET at the overdrive voltage of 0.5 V, respectively. What is more, better device performances are achieved by gate engineering with appropriate “In” fraction, proper space between the gate and source ( ${L}_{\text {gs}}$ ), and appropriate tunneling gate work function ( $\Phi _{\text {TG}}$ ). The direct-current, RF, and energy-efficient performance studies show that SSavg of 7.9 mV/dec, an on-state current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) of $\text {8.02} \times \text {10}^{-\text {5}}$ A/ $\mu \text{m}$ , a cutoff frequency ( ${f}_{T}$ ) of 119 GHz, and an energy delay product of 0.64 fJ-ps/ $\mu \text{m}$ can be obtained in the proposed TFET. This paper indicates that the gate engineered InGaN DL-TFET is a promising TFET for low-power RF and digital logic applications.

A High-Performance Gate Engineered InGaN Dopingless Tunnel FET

The interface region between Ga-face n-type GaN and Al2O3 dielectric (achieved via atomic-layer deposition or ALD) is investigated by X-ray photoelectron spectroscopy (XPS). An increase in the Ga-O to Ga-N bond intensity ratio following Al2O3 deposition implies that the growth of an interfacial gallium sub-oxide (GaOx) layer occurred during the ALD process. This finding may be ascribed to GaN oxidation, which may still happen following the reduction of a thin native GaOx by trimethylaluminum (TMA) in the initial TMA-only cycles. The valence band offset between GaN and Al2O3, obtained using both core-level and valence band spectra, is found to vary with the thickness of the deposited Al2O3. This observation may be explained by an upward energy band bending at the GaN surface (due to the spontaneous polarization induced negative bound charge on the Ga-face GaN) and the intrinsic limitation of the XPS method for band offset determination.

https://dr.ntu.edu.sg/bitstream/10356/100139/1/23.%20Interfacial%20chemistry%20and%20valence%20band%20offset%20between%20GaN%20and%20Al%202O3.pdf

Interfacial chemistry and valence band offset between GaN and Al2O3 studied by X-ray photoelectron spectroscopy

Gate-recessed AlGaN/AlN/GaN metal-oxide-semiconductor heterostructure high-mobility transistors (MOS-HEMTs) on SiC substrate are fabricated. The device with a gate length of 0.6 μm and a gate periphery of 100 μm exhibits a maximum dc drain current density of 1.59 A/mm at VGS = 3 V with an extrinsic transconductance (gm) of 374 mS/mm. An extrinsic current gain cutoff frequency (fT) of 19 GHz and a maximum oscillation frequency (fmax) of 50 GHz are deduced from S-parameter measurements. The output power density is 13 W/mm, and the associated power-added efficiency is 73% at 4-GHz frequency and 45-V drain bias. The power performance is comparable to state-of-the art AlGaN/GaN HEMTs, which demonstrates the great potential of gate-recessed MOS-HEMTs as a very promising alternative to GaN HEMTs.

High-Performance Microwave Gate-Recessed AlGaN/AlN/GaN MOS-HEMT With 73% Power-Added Efficiency

Ultrathin GeSn channels were epitaxially grown on Si(111) and (001) substrates using solid source molecular beam epitaxy. Well-behaved GeSn quantum well (QW) pTFETs and pMOSFETs were fabricated on Si. GeSn QW pMOSFETs on Si(111) demonstrate a high effective hole mobility of 505 cm2/Vs, indicating the high crystallinity of the GeSn material. GeSn QW pTFETs on Si(111) outperform the devices on Si(001) on subthreshold swing (SS) and ON-state current $I_{\mathrm{\scriptscriptstyle ON}}$ . (111)-oriented GeSn pTFET with a 4-nm-thick channel achieves a steep SS of $\sim 60$ mV/decade and a high ON-state/OFF-state current ratio of $10^{7}$ , which are superior to those of the other reported non-Si pTFETs with a small bandgap.

GeSn Quantum Well P-Channel Tunneling FETs Fabricated on Si(001) and (111) With Improved Subthreshold Swing

We design a GeSn/SiGeSn type-II staggered heterojunction n-channel tunneling FET (hetero-NTFET). The energy band structures of GeSn and SiGeSn alloys were calculated by utilizing the nonlocal empirical pseudopotential method. Staggered band alignment at $\Gamma $ -point for lattice-matched GeSn/SiGeSn is achieved by tuning the material compositions. The impact of a type-II tunneling junction (TJ) on the electrical performance of hetero-NTFET is investigated through a simulation using a TCAD simulator. Hetero-NTFET exhibits a negative shift of onset voltage $V_{\mathrm {ONSET}}$ , a steeper subthreshold swing, a higher on-state current $I_{\mathrm{\scriptscriptstyle ON}}$ , and a larger on-state current to off-state current ratio $ I_{\mathrm{\scriptscriptstyle ON}}/I_{\mathrm{\scriptscriptstyle OFF}}$ as compared with GeSn homojunction n-channel tunneling FET. A 3.4 times higher $I_{\mathrm{\scriptscriptstyle ON}}$ is achieved in Ge0.90Sn0.10/Si0.40Ge0.40Sn0.20 hetero-NTFET in comparison with Ge0.90Sn0.10 homo device at $V_{\mathrm {DD}}$ of 0.3 V. A hetero-NTFET exhibits a more abrupt hole profile and a higher hole concentration in a source region near the TJ compared with the homo device due to the presence of the hetero TJ. This contributes to the significantly enhanced band-to-band tunneling rate and tunneling current in the hetero-NTFET.

Theoretical Investigation of Performance Enhancement in GeSn/SiGeSn Type-II Staggered Heterojunction Tunneling FET

The invention discloses a high electron mobility transistor, and mainly solves the problems of serious current collapse and high source/drain ohmic contact resistance in the prior art From bottom to top, the high electron mobility transistor comprises a substrate (1), a nucleation layer (2), a main channel layer (3), a barrier layer (4) and a dielectric layer (13), wherein both sides of the top end of the barrier layer (4) are respectively provided with a source (10) and a drain (12), and the middle of the top end of the barrier layer (4) is provided with a gate (11); an auxiliary channel layer (5), a graded barrier layer (6), a high barrier layer (7), an isolation channel layer (8) and an isolation barrier layer (9) are sequentially added onto the barrier layer (4); the gate (11) is positioned in a groove (14) between the barrier layer and the isolation barrier layer; and both sides and the bottom of the gate are respectively provided with the dielectric layer (13) Two-dimensional electron gas (2DEG) is respectively formed on the interface of the isolation barrier layer and isolation channel layer, the interface of the graded barrier layer and auxiliary channel layer, and the interface of the barrier layer and main channel layer The invention can avoid current collapse under high field stress and reduce the source/drain ohmic contact resistance, and can be used as a high-temperature high-frequency high-reliability high-power device

High electron mobility transistor

The invention discloses a groove-shaped channel AlGaN/GaN-reinforced high electron mobility transistor (HEMT) component and a manufacturing method thereof and mainly solves the problem of low reliability caused by a low threshold voltage of the conventional reinforced component and large etching damage in the manufacturing process. The component comprises a substrate, an I-GaN layer, a II-GaN layer, an AlGaN barrier layer, a source, a drain, a medium layer and a grid from the bottom up, wherein a groove (1) is formed in the middle of the I-GaN layer so as to form a two-dimensional electronic gas (2DEG) on the planar interface between the II-GaN and the AlGaN, while the 2DEG cannot be formed on an inclining interface between the II-GaN and the AlGaN. According to different processes, the reinforced component structure can be manufactured into two types of components, namely a metal oxide semiconductor grid and a Schottky grid. The invention has the advantages of high reliability, simple process and good repeatability and can be used in high-temperature, high-frequency and large-power places, large-power switches and digital circuits.

Jincheng Zhang

Papers

High-Performance Microwave Gate-Recessed AlGaN/AlN/GaN MOS-HEMT With 73% Power-Added Efficiency

GeSn Quantum Well P-Channel Tunneling FETs Fabricated on Si(001) and (111) With Improved Subthreshold Swing

Theoretical Investigation of Performance Enhancement in GeSn/SiGeSn Type-II Staggered Heterojunction Tunneling FET

High electron mobility transistor

Groove-shaped channel AlGaN/GaN-reinforced high electron mobility transistor (HEMT) component and manufacturing method thereof