The science and technology of ultracapacitors are reviewed for a number of electrode materials, including carbon, mixed metal oxides, and conducting polymers. More work has been done using microporous carbons than with the other materials and most of the commercially available devices use carbon electrodes and an organic electrolytes. The energy density of these devices is 3¯5 Wh/kg with a power density of 300¯500 W/kg for high efficiency (90¯95%) charge/discharges. Projections of future developments using carbon indicate that energy densities of 10 Wh/kg or higher are likely with power densities of 1¯2 kW/kg. A key problem in the fabrication of these advanced devices is the bonding of the thin electrodes to a current collector such the contact resistance is less than 0.1 cm2. Special attention is given in the paper to comparing the power density characteristics of ultracapacitors and batteries. The comparisons should be made at the same charge/discharge efficiency.

Ultracapacitors: Why, How, and Where is the Technology

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Before the emergence of ultra-wideband (UWB) radios, widely used wireless communications were based on sinusoidal carriers, and impulse technologies were employed only in specific applications (e.g. radar). In 2002, the Federal Communication Commission (FCC) allowed unlicensed operation between 3.1–10.6 GHz for UWB communication, using a wideband signal format with a low EIRP level (−41.3dBm/MHz). UWB communication systems then emerged as an alternative to narrowband systems and significant effort in this area has been invested at the regulatory, commercial, and research levels.

IEEE Transactions on Microwave Theory and Techniques and Antennas and Propagation Announce a Joint Special Issue on Ultra-Wideband (UWB) Technology

IEEE transactions on very large scale integration (VLSI) systems

Wireless power transmission was conceptualized nearly a century ago. Certain achievements made to date have made power harvesting a reality, capable of providing alternative sources of energy. This review provides a summ ary of radio frequency (RF) power harvesting technologies in order to serve as a guide for the design of RF energy harvesting units. Since energy harvesting circuits are designed to operate with relatively small voltages and currents, they rely on state-of-the-art electrical technology for obtaining high efficiency. Thus, comprehensive analysis and discussions of various designs and their tradeoffs are included. Finally, recent applications of RF power harvesting are outlined.

/pdf/rf-power-harvesting-a-review-on-designing-methodologies-and-a28105yvyi.pdf

RF power harvesting: a review on designing methodologies and applications

A power-efficient frequency compensation topology, Impedance Adapting Compensation (IAC), is presented in this paper. This IAC topology has, on one hand, a normal Miller capacitor, which is still needed to provide an internal negative feedback loop, and on the other hand, a serial RC impedance as a load to the intermediate stage, improving performance parameters such as stability, gain-bandwidth product and power dissipation. A three-stage IAC amplifier was implemented and fabricated in a 0.35 μm CMOS technology. Experiment results show that the implemented IAC amplifier, driving a 150 pF load capacitance, achieved a gain-bandwidth product (GBW) of 4.4 MHz while dissipating only 30 μW power with a 1.5 V supply.

Impedance Adapting Compensation for Low-Power Multistage Amplifiers

The Network-on-Chip (NoC) has been recognized as a paradigm to solve System-on-Chip (SoC) design challenges. The routing algorithm is one of key researches of a NoC design. XY routing algorithm, which is a kind of distributed deterministic routing algorithms, is simple to be implemented. Odd-Even (OE) routing algorithm, whose implementation is complex, is a sort of distributed adaptive routing algorithms with deadlock-free ability. We demonstrate the two routing algorithms in details at first. XY routing algorithm and OE routing algorithm are then simulated and compared based on a 3X3 mesh topology NoC with NIRGAM simulator. The simulation results show that OE routing algorithm, whose P parameter equals to 1.09, increases P parameter greatly as compared to XY routing algorithm, whose P parameter equals to 0.86, in a 2-dimension 3X3 mesh topology NoC, with Constant Bit Rate (CBR) traffic condition of each tail.

Comparison Research between XY and Odd-Even Routing Algorithm of a 2-Dimension 3X3 Mesh Topology Network-on-Chip

https://www.ndsu.edu/pubweb/~nagong/index_files/journal/J7.pdf

Analysis and optimization of leakage current characteristics in sub-65nm dual Vt footed domino circuits

Low power and high performance dynamic CMOS XOR/XNOR gate design

Memristors offer advantages as a hardware solution for neuromorphic computing, and however, their nonlinear device property makes the weight update inaccurately and reduces the recognition accuracy of a neural network. In this paper, a piecewise linear (PL) method is proposed to mitigate the nonlinear effect of memristors by calculating the weight update parameters along a piecewise line, which reduces the errors in the weight update process. It mitigates the nonlinearity impact without reading the precise conductance of the memristor in each updating step, thereby avoiding complex peripheral circuits. The effectiveness of the proposed PL method with 2-segment, 3-segment, and 4-segment models in two split selection strategies is investigated, and the impact of various variations is considered. The results show that under different nonlinearities, the PL method can increase the recognition accuracy of the Modified National Institute of Standards and Technology (MNIST) handwriting digits to 87.87%–95.05% compared with 10.77%–73.18% of the cases without the PL method.

Jinhui Wang

Papers

Impedance Adapting Compensation for Low-Power Multistage Amplifiers

Comparison Research between XY and Odd-Even Routing Algorithm of a 2-Dimension 3X3 Mesh Topology Network-on-Chip

Analysis and optimization of leakage current characteristics in sub-65nm dual Vt footed domino circuits

Low power and high performance dynamic CMOS XOR/XNOR gate design

Mitigating Nonlinear Effect of Memristive Synaptic Device for Neuromorphic Computing