Soo-In Cho

TL;DR: This paper describes a dual-loop delay-locked loop (DLL) which overcomes the problem of a limited delay range by using multiple voltage-controlled delay lines (VCDLs).

TL;DR: In this article, the self and mutual capacitance and inductance of coupled microstrip lines in a printed circuit board were derived from the numerical simulation results to reduce the computation time for crosstalk estimation.

TL;DR: Two design techniques are presented to improve the yield of high density DRAM product using bit line coupling (BLC) scheme and the E-Fuse circuit for reliable field programmable repair scheme.

TL;DR: The proposed DBI circuit uses an analog majority voter insensitive to mismatch for small area and delay, and a dual duty cycle corrector (DCC) is used to reduce duty error and jitter by averaging two outputs of two DCCs.

TL;DR: A DRAM interface operating at 3.6 Gb/s/pin implemented in 130-nm CMOS logic and 110-nm DRAM process technologies utilizes simultaneous bidirectional signaling in a daisy-chained, point-to-point configuration to enable high performance scalable memory subsystems and also provides direct attach capability for DRAMs to memory controllers or other logic devices.