J
John A. Fitzsimmons
Researcher at IBM
Publications - 98
Citations - 1323
John A. Fitzsimmons is an academic researcher from IBM. The author has contributed to research in topics: Layer (electronics) & Dielectric. The author has an hindex of 19, co-authored 98 publications receiving 1319 citations. Previous affiliations of John A. Fitzsimmons include GlobalFoundries.
Papers
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Patent
Method for forming patterned films on a substrate
TL;DR: In this paper, the photo resist underlayer was removed using a selective photo resist stripper composition and the structure was then blanketed with a conductive layer to create conductive contact stud.
Patent
Exposed pore sealing post patterning
Edward C. Cooney,John A. Fitzsimmons,Jeffrey P. Gambino,Stephen E. Luce,Thomas L. McDevitt,Lee M. Nicholson,Anthony K. Stamper +6 more
TL;DR: In this article, a pore-closing layer was proposed for closed exposed pores in a patterned porous low-k dielectric layer, and a reactive lintern was formed on the lintern.
Patent
Device and methodology for reducing effective dielectric constant in semiconductor devices
Daniel C. Edelstein,Matthew E. Colburn,Edward C. Cooney,Timothy J. Dalton,John A. Fitzsimmons,Jeffrey P. Gambino,Elbert E. Huang,Michael Lane,Vincent J. McGahay,Lee M. Nicholson,Satyanarayana V. Nitta,Sampath Purushothaman,Sujatha Sankaran,Thomas M. Shaw,Andrew H. Simon,Anthony K. Stamper +15 more
TL;DR: Semiconductor structure includes an insulator layer having at least one interconnect feature and at least 1 gap formed in the insulator layers spanning more than a minimum spacing of interconnects as mentioned in this paper.
Patent
Advanced BEOL interconnect structures with low-k PE CVD cap layer and method thereof
Edward Barth,John A. Fitzsimmons,Stephen M. Gates,T. H. Ivers,Sarah L. Lane,Jia Lee,Ann Mcdonald,Vincent J. McGahay,Darryl D. Restaino +8 more
TL;DR: In this paper, an advanced back-end-of-line (BEOL) metallization structure is disclosed, which includes a diffusion barrier or cap layer having a low dielectric constant (low-k), where the cap layer is formed of silicon nitride by a plasma enhanced chemical vapor deposition (PE CVD) process.
Proceedings ArticleDOI
High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL
Woo-Hyeong Lee,A. Waite,H. Nii,Hasan M. Nayfeh,Vincent J. McGahay,H. Nakayama,David M. Fried,H. Chen,Linda Black,R. Bolam,J. Cheng,Dureseti Chidambarrao,Cathryn Christiansen,M. Cullinan-Scholl,D.R. Davies,Anthony G. Domenicucci,P. Fisher,John A. Fitzsimmons,Jason Gill,Michael A. Gribelyuk,D. Harmon,Judson R. Holt,K. Ida,M. Kiene,J. Kluth,C. Labelle,Anuj Madan,K. Malone,P.V. McLaughlin,M. Minami,Dan Mocuta,R. Murphy,Christopher D. Muzzy,M. Newport,Siddhartha Panda,I. Peidous,A. Sakamoto,T. Sato,G. Sudo,H. VanMeer,Tenko Yamashita,H. Zhu,Paul D. Agnello,Gary B. Bronner,Gregory G. Freeman,S.-F. Huang,T. H. Ivers,Scott Luning,K. Miyamoto,Henry A. Nye,J. Pellerin,K. Rim,Dominic J. Schepis,Spooner Terry A,X. Chen,Mukesh Khare,Manfred Horstmann,A. Wei,Thorsten Kammler,J. Hontschel,Helmut Bierstedt,Hans-Jürgen Engelmann,A. Hellmich,K. Hempel,Guido Koerner,A. Neu,Ralf Otterbach,C. Reichel,M. Trentsch,Patrick Press,Kai Frohberg,Matthias Schaller,Heike Salz,Jörg Hohage,Hartmut Ruelke,J. Klais,Michael Raab,D. Greenlaw,N. Kepler +78 more
TL;DR: In this paper, a high performance 65 nm SOI CMOS technology is presented with dual stress liner (DSL), embedded SiGe, and stress memorization techniques utilized to enhance transistor speed Advanced low-K BEOL for this technology features 10 wiring levels with a novel K=275 film in selected levels.