M
Mukesh Khare
Researcher at IBM
Publications - 76
Citations - 2529
Mukesh Khare is an academic researcher from IBM. The author has contributed to research in topics: CMOS & Metal gate. The author has an hindex of 25, co-authored 76 publications receiving 2137 citations.
Papers
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Proceedings ArticleDOI
Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
Nicolas Loubet,Terence B. Hook,Pietro Montanini,Chun Wing Yeung,S. Kanakasabapathy,M. Guillom,Tenko Yamashita,Jingyun Zhang,Xin Miao,Junli Wang,Albert M. Young,Robin Chao,Myounggon Kang,Zuoguang Liu,Su Chen Fan,Bassem Hamieh,Stuart A. Sieg,Yann Mignot,W. Xu,Soon-Cheon Seo,Jae-Yoon Yoo,Shogo Mochizuki,Muthumanickam Sankarapandian,Ohyun Kwon,Adra Carr,Andrew M. Greene,Young-Kwan Park,Frougier Julien,Rohit Galatage,Ruqiang Bao,Jeffrey C. Shearer,Richard A. Conti,Ho Ju Song,Deok-Hyung Lee,Dexin Kong,Y. Xu,Abraham Arceo,Zhenxing Bi,Peng Xu,Raja Muthinti,James Chingwei Li,Robert C. Wong,D. Brown,P. Oldiges,Robert R. Robison,John C. Arnold,Nelson Felix,Spyridon Skordas,John G. Gaudiello,Theodorus E. Standaert,Hemanth Jagannathan,D. Corliss,Myung-Hee Na,Andreas Knorr,T. Wu,Dinesh Gupta,S. Lian,R. Divakaruni,T. Gow,C. Labelle,Seng Luan Lee,Vamsi Paruchuri,Huiming Bu,Mukesh Khare +63 more
TL;DR: In this paper, the authors demonstrate that horizontally stacked gate-all-around (GAA) nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond.
Proceedings ArticleDOI
High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography
Shreesh Narasimha,Katsunori Onishi,Hasan M. Nayfeh,A. Waite,M. Weybright,Jeffrey B. Johnson,Carlos A. Fonseca,D. Corliss,C. Robinson,Michael Crouse,D. Yang,C-H.J. Wu,Allen H. Gabor,Thomas N. Adam,Ishtiaq Ahsan,Michael P. Belyansky,L. Black,Shahid Butt,J. Cheng,Anthony I. Chou,G. Costrini,Christos D. Dimitrakopoulos,Anthony G. Domenicucci,P. Fisher,A. Frye,S. Gates,Stephen E. Greco,Stephan Grunow,M. Hargrove,Judson R. Holt,S.-J. Jeng,M. Kelling,B. Kim,William F. Landers,G. Larosa,D. Lea,Ming-Hsiu Lee,X. Liu,Naftali E. Lustig,A. McKnight,L. Nicholson,D. Nielsen,Karen A. Nummy,Viorel Ontalus,C. Ouyang,X. Ouyang,C. Prindle,R. Pal,Werner A. Rausch,D. Restaino,Christopher D. Sheraw,J. Sim,Andrew H. Simon,Theodorus E. Standaert,Chun-Yung Sung,Keith H. Tabakman,C. Tian,R. Van Den Nieuwenhuizen,H. van Meer,A. Vayshenker,Deepal Wehella-Gamage,J. Werking,R. C. Wong,S. Wu J. Yu,R. Augur,D. Brown,X. Chen,Daniel C. Edelstein,A. Grill,Mukesh Khare,Yujun Li,S. Luning,J. Norum,Sujatha Sankaran,Dominic J. Schepis,Richard A. Wachnik,Richard Wise,C. Wann,T. Ivers,Paul D. Agnello +79 more
TL;DR: In this paper, the authors present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule scaling enabled by 1.2NA/193nm immersion lithography, ii) high-performance FET response enabled by the integration of multiple advanced strain and activation techniques, iii) a functional SRAM with cell size of 0.37mum2, and iv) a porous low-k (k=2.4) dielectric for minimized back-end wiring delay.
Proceedings ArticleDOI
A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process
X. Chen,S. Samavedam,Vijay Narayanan,Kenneth J. Stein,C. Hobbs,Christopher V. Baiocco,Weipeng Li,Jaeger Daniel,M. Zaleski,Haining Yang,Nam-Sung Kim,Yi-Wei Lee,Da Zhang,Laegu Kang,J. Chen,Haoren Zhuang,Arifuzzaman (Arif) Sheikh,J. Wallner,Michael V. Aquilino,Jin-Ping Han,Zhenrong Jin,James Chingwei Li,G. Massey,S. Kalpat,Rashmi Jha,Naim Moumen,R. Mo,S. Kirshnan,X. Wang,Michael P. Chudzik,M. Chowdhury,Deleep R. Nair,C. Reddy,Young Way Teh,Chandrasekharan Kothandaraman,Douglas D. Coolbaugh,Shesh Mani Pandey,D. Tekleab,Aaron Thean,Melanie J. Sherony,Craig S. Lage,J. Sudijono,R. Lindsay,JiYeon Ku,Mukesh Khare,An L. Steegen +45 more
TL;DR: In this article, a 32 nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mum2 was demonstrated.
Proceedings ArticleDOI
A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
Siddarth A. Krishnan,Unoh Kwon,Naim Moumen,Matthew W. Stoker,Eric C. Harley,Stephen W. Bedell,Deleep R. Nair,B. Greene,William K. Henson,Murshed M. Chowdhury,D.P. Prakash,Ernest Y. Wu,Dimitris P. Ioannou,Eduard A. Cartier,Myung-Hee Na,S. Inumiya,Kevin McStay,Lisa F. Edge,Ryosuke Iijima,Jin Cai,Martin M. Frank,M. Hargrove,Dechao Guo,Andreas Kerber,Hemanth Jagannathan,Takashi Ando,Joseph F. Shepard,Shahab Siddiqui,Min Dai,Huiming Bu,J. Schaeffer,Jaeger Daniel,Kathy Barla,Thomas A. Wallner,S. Uchimura,Y. Lee,Gauri Karve,Sufi Zafar,Dominic J. Schepis,Yun-Yu Wang,Ricardo A. Donaton,S. Saroop,P. Montanini,Yue Liang,James H. Stathis,Richard Carter,Rohit Pal,Vamsi Paruchuri,H. Yamasaki,J-H Lee,Martin Ostermayr,J.-P. Han,Yue Hu,Michael A. Gribelyuk,Dae-Gyu Park,X. Chen,Srikanth Samavedam,Shreesh Narasimha,Paul D. Agnello,Mukesh Khare,R. Divakaruni,Vijay Narayanan,Michael P. Chudzik +62 more
TL;DR: In this article, the authors leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) high-к/metal gate (HKMG) logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.
Proceedings ArticleDOI
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
Ruilong Xie,Pietro Montanini,Kerem Akarvardar,Neeraj Tripathi,Balasubramanian S. Pranatharthi Haran,Scott C. Johnson,Terence B. Hook,Bassem Hamieh,D. Corliss,Junli Wang,Xin Miao,John R. Sporre,Jody A. Fronheiser,Nicolas Loubet,Min Gyu Sung,Stuart A. Sieg,Shogo Mochizuki,Christopher Prindle,Soon-Cheon Seo,Andrew M. Greene,Jeffrey C. Shearer,Andre Labonte,Su Chen Fan,Lars W. Liebmann,Robin Chao,Abraham Arceo,Kisup Chung,K. Cheon,Praneet Adusumilli,H. P. Amanapu,Zhenxing Bi,Jungho Cha,H. Chen,Richard A. Conti,Rohit Galatage,Oleg Gluschenkov,Vimal Kamineni,Ki-chul Kim,Lee Choonghyun,F. Lie,Zuoguang Liu,Sanjay Mehta,Eric R. Miller,Hiroaki Niimi,Chengyu Niu,Chanro Park,D. Park,Mark Raymond,Bhagawan Sahu,Muthumanickam Sankarapandian,Shariq Siddiqui,Richard G. Southwick,Lei Sun,Charan V. V. S. Surisetty,Stan D. Tsai,S. Whang,Peng Xu,Y. Xu,C.-C. Yeh,Peter Zeitzoff,J. Zhang,James Chingwei Li,James J. Demarest,John C. Arnold,Donald F. Canaperi,Derren N. Dunn,Nelson Felix,Dinesh Gupta,Hemanth Jagannathan,S. Kanakasabapathy,Walter Kleemeier,C. Labelle,M. Mottura,P. Oldiges,Spyridon Skordas,Theodorus E. Standaert,Tenko Yamashita,Matthew E. Colburn,Myung-Hee Na,Vamsi Paruchuri,S. Lian,R. Divakaruni,T. Gow,Seng Luan Lee,Andreas Knorr,Huiming Bu,Mukesh Khare +86 more
TL;DR: In this paper, the authors present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology.