We present a comprehensive, up-to-date compilation of band parameters for the technologically important III–V zinc blende and wurtzite compound semiconductors: GaAs, GaSb, GaP, GaN, AlAs, AlSb, AlP, AlN, InAs, InSb, InP, and InN, along with their ternary and quaternary alloys. Based on a review of the existing literature, complete and consistent parameter sets are given for all materials. Emphasizing the quantities required for band structure calculations, we tabulate the direct and indirect energy gaps, spin-orbit, and crystal-field splittings, alloy bowing parameters, effective masses for electrons, heavy, light, and split-off holes, Luttinger parameters, interband momentum matrix elements, and deformation potentials, including temperature and alloy-composition dependences where available. Heterostructure band offsets are also given, on an absolute scale that allows any material to be aligned relative to any other.

Band parameters for III–V compound semiconductors and their alloys

Over the past three decades a new spectroscopic technique with unique possibilities has emerged. Based on coherent and time-resolved detection of the electric field of ultrashort radiation bursts in the far-infrared, this technique has become known as terahertz time-domain spectroscopy (THz-TDS). In this review article the authors describe the technique in its various implementations for static and time-resolved spectroscopy, and illustrate the performance of the technique with recent examples from solid-state physics and physical chemistry as well as aqueous chemistry. Examples from other fields of research, where THz spectroscopic techniques have proven to be useful research tools, and the potential for industrial applications of THz spectroscopic and imaging techniques are discussed.

Terahertz spectroscopy and imaging – Modern techniques and applications

The scaling of complementary metal oxide semiconductor transistors has led to the silicon dioxide layer, used as a gate dielectric, being so thin (14?nm) that its leakage current is too large It is necessary to replace the SiO2 with a physically thicker layer of oxides of higher dielectric constant (?) or 'high K' gate oxides such as hafnium oxide and hafnium silicate These oxides had not been extensively studied like SiO2, and they were found to have inferior properties compared with SiO2, such as a tendency to crystallize and a high density of electronic defects Intensive research was needed to develop these oxides as high quality electronic materials This review covers both scientific and technological issues?the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure and reactions, their electronic structure, bonding, band offsets, electronic defects, charge trapping and conduction mechanisms, mobility degradation and flat band voltage shifts The oxygen vacancy is the dominant electron trap It is turning out that the oxides must be implemented in conjunction with metal gate electrodes, the development of which is further behind Issues about work function control in metal gate electrodes are discussed

https://iopscience.iop.org/article/10.1088/0034-4885/69/2/R02/pdf

High dielectric constant gate oxides for metal oxide Si transistors

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin (1.4 nm) that its leakage current is too large. It is necessary to replace the SiO2 with a physically thicker layer of oxides of higher dielectric constant (κ) or 'high K' gate oxides such as hafnium oxide and hafnium silicate. Little was known about such oxides, and it was soon found that in many respects they have inferior electronic properties to SiO2 ,s uch as a tendency to crystallise and a high concentration of electronic defects. Intensive research is underway to develop these oxides into new high quality electronic materials. This review covers the choice of oxides, their structural and metallurgical behaviour, atomic diffusion, their deposition, interface structure and reactions, their electronic structure, bonding, band offsets, mobility degradation, flat band voltage shifts and electronic defects. The use of high K oxides in capacitors of dynamic random access memories is also covered.

/pdf/high-dielectric-constant-oxides-cotu2e70vd.pdf

High dielectric constant oxides

There has been much recent progress on both the theoretical understanding of the electronic structure of idealized III-V semiconductor surfaces and interfaces and the UHV characterization of real surfaces and interfaces. However, except for a few cases, this knowledge is insufficient to adequately explain the optical and electrical behavior of surfaces and interfaces used in practical devices. For example, information obtained from monolayer and submonolayer depositions in UHV conditions on cleaved (I 10) surfaces, although useful, does not lead to a fundamental understanding of such device properties as Schottky barrier height, Ohmic contact resistance, and surface recombination velocities. One reason for this is that the interpretation of UHV results is complicated by the difficulty of differentiating between metallurgical, e.g., interface chemistry, and structural, e.g., surface defects, effects which occur simultaneously during deposition. Another reason is that practical devices are made on (100) surfaces whereas most of the UHV work has been on (110) surfaces, and it is well known that the \"clean\" versions of these surfaces are both structurally and electronically different. Finally, there are problems in relating the experimental results of measurements such as I-V, C-V, XPS, and photoemission to concepts such as barrier height, electron affinity, work function, surface states, and surface energy levels. Let us compare some interface models with experimental data, especially with respect to the variation of surface and interface properties with surface treatment. We know, for example, that GaAs( 110) surfaces formed by cieaving in UHV are free of surface states which lie in the direct gap. I Thus, the Fermi level at the surface is the same as that for the bulk. Theory and experiment are reconciled on this issue. To date it appears that all other gas or vacuum/GaAs surfaces have a surface Fermi level which is pinned roughly at midgap. In fact, the results of UHV experiments on (110) surfaces with submonolayer coverage of a variety of adatoms suggest that there may be two levels, a deep acceptor and a deep donor, which are associated with surface defects which are responsible for the pinning. 2 It has been known for some time that Schottky barriers to GaAs cannot be directly explained by the Schottky work function model, i.e., the barrier height is not proportional to the work function of the applied metallurgy. This coupled with the UHV pinning results has led to the hypothesis that the fundamental mechanism of Schottky barrier formation for metallGaAS interfaces used in solid state devices is Fermi level pinning due to surface defects. 3 At first glance this model appears compelling since the pinning positions are within 0.1 eV of the barrier heights commonly quoted in textbooks. However, there is a problem with reconciling the predictions of a two energy level, i.e., two pinning position, surface defect model with experimental observations that in some cases, the sum of the p-type and n-type barrier heights equals the band gap energy. A recent attempt to resolve this problem shows that in order to reconcile these observations with the defect models, a surface defect density of at least o. I monolayers is required. At this density the barrier height is only a weak function of the metal work function. Therefore, the observed midgap barrier heights can be explained by juggling the deep level defect density and the metal work function. Thus, it is beginning to appear that barrier heights at metallGaAs interfaces can be explained in terms of a coupled interaction between the electronic properties of a dominant surface effect, e.g., vacancies, antisite defects, clusters, MIGS, surface reconstruction, etc., and the electronic properties of the applied metallurgy, e.g., the work function. The task is to identify the dominant surface effect(s) and to relate their occurrence to surface preparation and metallization method. The nature of the dominant surface effect is by no means resolved. There are many observations which tend to rule out deep level surface vacancies or antisite-type defects as the dominant surface effect. 5 For example, the Pd/GaAs interfaces for which the Fermi level is not at pinned midgap. 5 Furthermore, for the two level defect models, two distinct regions of almost constant barrier height (each corresponding to one pinning defect) should be observed as a function of the metal work function. 4 This may have been seen for InP,6 but not for GaAs as yet. There are, in fact, observed barrier heights, e.g., for All AlAs formed by MBE,7 which are adequately explained by the simple work function model, i.e., the Al work function and AlAs electron affinity, and with no defect levels required. Also, there is the following paradox: (1) it takes 0.1 monolayers of deep level defects to pin the Fermi level at midgap and produce the observed barrier heights; (2) these defects are produced by metallization from thermal beams; (3) the Schottky barriers, and hence the defect density, are stable to an 800 °C anneal; (4) this surface defect density corresponds to a volume density of 10 cm 3; (5) layers grown by the MBE method using thermal beams have volume defect densities of only 1013 cm 3 or less. How is this defect density reduced by eight orders of magnitude for MBE grown layers and not for annealed metallGaAs interfaces? Thus, a theoretical framework which requires the surface effects to be deep, multiJeveled, and of opposite conductivity type seems too restrictive in view of the wide var-

Summary Abstract: Surface treatment and interface properties: What really matters?

Surface scientists argue about the fundamental nature of Schottky barriers, or more precisely what determines the location of the Fermi level at semiconductor surfaces and interfaces. Electrical and materials engineers worry about how to make Schottky barrier diodes and gates to field effect transistors and the control of barrier heights. There is some interesting middle ground in which the location of the surface and interface Fermi level can, for example, determine semiconductor doping characteristics during crystal growth. In keeping with the trendy fashion of the 80’s to invent ‘‘catchy phrases’’ to describe marginally important new fields, we dub this middle ground as ‘‘surface Fermi level engineering.’’ Within the framework of this concept, we will discuss several interesting and well known examples of doping characteristics which are still somewhat mysterious. Specifically, we will address the following questions: (1) why is Ge doped GaAs p type when grown from Ga melts but n type when grown from A...

Surface Fermi level engineering: Or there is more to Schottky barriers than just making diodes and field effect transistor gates

The experimental observations of metallurgical interactions between compound semiconductor substrates and metallic or oxide overlayers have stimulated a new model of Fermi level ’’pinning’’ at these interfaces. This model assumes the standard Schottky picture of interface band alignment, but that the interface phases involved are not the pure metal or oxide normally assumed by other models. For both III‐V and II‐VI compounds, the barrier height to gold is found to correlate well with the anion work function, suggesting the interface phases are often anion rich. This correlation holds even for cases in which the ’’common anion rule’’ fails, and explains both successes and failures of this earlier model.

Schottky barriers: An effective work function model

We report noncontact measurements of the effective minority carrier lifetime in the superficial silicon layer of silicon‐on‐insulator wafers. The carriers are excited by a pulse of short‐wavelength photons (λ≤350 nm), all of which are absorbed in the first 500 A of the silicon layer. The carriers are detected by the change in microwave reflectance in a resonant circuit to which the wafer is coupled. The results obtained vary from ∼3 μs for a three year old separation by implanted oxygen (SIMOX) wafer to ∼25 μs for current vendor SIMOX and bond‐etchback samples. The variation in free surface recombination velocity is eliminated by HF passivating the samples prior to measurement.

Lifetime measurements on silicon‐on‐insulator wafers

An electrical device which employs two-dimensional space charge modulation in a semiconductor structure. The device has an approximately Debye length wide contact and a rectifying contact positioned adjacent to each other within a Debye length on a semiconductor body and a contact remotely positioned. A bias on the rectifying contact will effect conduction between the other contacts.

John L. Freeouf

Papers

Summary Abstract: Surface treatment and interface properties: What really matters?

Surface Fermi level engineering: Or there is more to Schottky barriers than just making diodes and field effect transistor gates

Schottky barriers: An effective work function model

Lifetime measurements on silicon‐on‐insulator wafers

Space charge modulation device