We present a comprehensive, up-to-date compilation of band parameters for the technologically important III–V zinc blende and wurtzite compound semiconductors: GaAs, GaSb, GaP, GaN, AlAs, AlSb, AlP, AlN, InAs, InSb, InP, and InN, along with their ternary and quaternary alloys. Based on a review of the existing literature, complete and consistent parameter sets are given for all materials. Emphasizing the quantities required for band structure calculations, we tabulate the direct and indirect energy gaps, spin-orbit, and crystal-field splittings, alloy bowing parameters, effective masses for electrons, heavy, light, and split-off holes, Luttinger parameters, interband momentum matrix elements, and deformation potentials, including temperature and alloy-composition dependences where available. Heterostructure band offsets are also given, on an absolute scale that allows any material to be aligned relative to any other.

Band parameters for III–V compound semiconductors and their alloys

Over the past three decades a new spectroscopic technique with unique possibilities has emerged. Based on coherent and time-resolved detection of the electric field of ultrashort radiation bursts in the far-infrared, this technique has become known as terahertz time-domain spectroscopy (THz-TDS). In this review article the authors describe the technique in its various implementations for static and time-resolved spectroscopy, and illustrate the performance of the technique with recent examples from solid-state physics and physical chemistry as well as aqueous chemistry. Examples from other fields of research, where THz spectroscopic techniques have proven to be useful research tools, and the potential for industrial applications of THz spectroscopic and imaging techniques are discussed.

Terahertz spectroscopy and imaging – Modern techniques and applications

The scaling of complementary metal oxide semiconductor transistors has led to the silicon dioxide layer, used as a gate dielectric, being so thin (14?nm) that its leakage current is too large It is necessary to replace the SiO2 with a physically thicker layer of oxides of higher dielectric constant (?) or 'high K' gate oxides such as hafnium oxide and hafnium silicate These oxides had not been extensively studied like SiO2, and they were found to have inferior properties compared with SiO2, such as a tendency to crystallize and a high density of electronic defects Intensive research was needed to develop these oxides as high quality electronic materials This review covers both scientific and technological issues?the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure and reactions, their electronic structure, bonding, band offsets, electronic defects, charge trapping and conduction mechanisms, mobility degradation and flat band voltage shifts The oxygen vacancy is the dominant electron trap It is turning out that the oxides must be implemented in conjunction with metal gate electrodes, the development of which is further behind Issues about work function control in metal gate electrodes are discussed

https://iopscience.iop.org/article/10.1088/0034-4885/69/2/R02/pdf

High dielectric constant gate oxides for metal oxide Si transistors

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin (1.4 nm) that its leakage current is too large. It is necessary to replace the SiO2 with a physically thicker layer of oxides of higher dielectric constant (κ) or 'high K' gate oxides such as hafnium oxide and hafnium silicate. Little was known about such oxides, and it was soon found that in many respects they have inferior electronic properties to SiO2 ,s uch as a tendency to crystallise and a high concentration of electronic defects. Intensive research is underway to develop these oxides into new high quality electronic materials. This review covers the choice of oxides, their structural and metallurgical behaviour, atomic diffusion, their deposition, interface structure and reactions, their electronic structure, bonding, band offsets, mobility degradation, flat band voltage shifts and electronic defects. The use of high K oxides in capacitors of dynamic random access memories is also covered.

/pdf/high-dielectric-constant-oxides-cotu2e70vd.pdf

High dielectric constant oxides

The conduction and valence band offsets between amorphous LaAlO3 and silicon have been determined from x-ray photoelectron spectroscopy measurements. These films, which are free of interfacial SiO2, were made by molecular-beam deposition. The band line-up is type I with measured band offsets of 1.8±0.2 eV for electrons and 3.2±0.1 eV for holes. The band offsets are independent of the doping concentration in the silicon substrate as well as the amorphous LaAlO3 film thickness. These amorphous LaAlO3 films have a bandgap of 6.2±0.1 eV.

/pdf/measurement-of-the-band-offsets-between-amorphous-laalo3-and-2j9yvsohme.pdf

Measurement of the band offsets between amorphous LaAlO3 and silicon

Atomic layer deposition has been employed to grow nanowires composed of ZnSe/CdSe superlattices. Growth of the nanowires was initiated using gold nanoparticles and the vapor-liquid-solid mechanism. High-resolution transmission electron microscopy shows that these structures are single crystals and the phase of alternating layers of ZnSe and CdSe is zinc blende. The (111) planes of ZnSe and CdSe are oriented at 60°.

Atomic layer deposition of ZnSe/CdSe superlattice nanowires

Ohmic and Schottky barrier contacts with desired properties are difficult to form on GaAs devices. This is due mainly to the fact that the position of the Fermi energy is loosely ’’pinned’’ near midgap for GaAs surfaces which are metallized using conventional techniques. Doped alloyed metal ohmic and refractory metal Schottky contacts formed on carefully cleaned surfaces are currently widely used. New contacting techniques including the use of lattice matched heterojunctions, nonalloyed n++ and p++ surfaces, graded band gap structures, and special surface treatment prior to metallization promise to provide both greater flexibility and control for future applications.

GaAs metallization: Some problems and trends

Computer simulations of mixed phase Schottky contacts have been performed to gain insight into the effects of lateral dimensions upon device behavior. As expected, lateral dimensions comparable to the Debye length of the semiconductor result in strong modification of the device characteristics that would result from independent, parallel diodes. We suggest that such effects can play a role in most experimentally obtained contacts. Current models of Schottky barrier formation typically invoke kinetics‐limited chemical interactions at the metal‐semiconductor interface; such effects are unlikely to be laterally uniform over macroscopic dimensions, and may well provide strong sensitivity to seemingly minor variations in preparation techniques used by different groups. We demonstrate that mixed phase contacts, with size effects, can affect ideality factors, and can also cause disagreement between C‐V and I‐V barrier heights.

Effective barrier heights of mixed phase contacts: Size effects

Deposition of nickel silicide nanowires has been achieved in the temperature range of 320 to 420 °C by decomposition of silane on nickel surfaces. The substrates consisted of Ni foils and thin Ni films (∼10–100 nm) evaporated on 1-μm-thick layers of SiO2 predeposited on Si wafers. Nanowire growth between two metal pads was achieved with aid of an electric field. It was found that thinner diameter nanowires were produced at low temperatures and that the density of the nanowires was dependent on the reactor pressure. The current–voltage relationship of these nanowires has also been examined.

http://web.pdx.edu/~jfreeouf/Freeouf%20Publications/Deccker_APL_84_1389_2004.pdf

John L. Freeouf

Papers

Measurement of the band offsets between amorphous LaAlO3 and silicon

Atomic layer deposition of ZnSe/CdSe superlattice nanowires

GaAs metallization: Some problems and trends

Effective barrier heights of mixed phase contacts: Size effects

Directed growth of nickel silicide nanowires