Showing papers by "John W. Palmour published in 2013"

15 kV, Large Area (1 cm 2 ), 4H-SiC p-Type Gate Turn-Off Thyristors

Abstract: In this paper, we report our recently developed 1 cm2, 15 kV SiC p-GTO with an extremely low differential on-resistance (RON,diff) of 4.08 mΩ•cm2 at a high injection-current density (JAK) of 600 ~ 710 A/cm2. The 15 kV SiC p-GTO was built on a 120 μm, 2×1014/cm3 doped p-type SiC drift layer with a device active area of 0.521 cm2. Forward conduction of the 15 kV SiC p-GTO was characterized at 20°C and 200°C. Over this temperature range, the RON,diff at JAK of 600 ~ 710 A/cm2 decreased from 4.08 mΩ•cm2 at 20°C to 3.45 mΩ•cm2 at JAK of 600 ~ 680 A/cm2 at 200°C. The gate to cathode blocking voltage (VGK) was measured using a customized high-voltage test set-up. The leakage current at a VGK of 15 kV were measured 0.25 µA and 0.41 µA at 20°C and 200°C respectively.

Monolithically integrated vertical power transistor and bypass diode

Abstract: A vertical field-effect transistor (FET) device includes a monolithically integrated bypass diode connected between a source contact and a drain contact of the vertical FET device. According to one embodiment, the vertical FET device includes a pair of junction implants separated by a junction field-effect transistor (JFET) region. At least one of the junction implants of the vertical FET device includes a deep well region that is shared with the integrated bypass diode, such that the shared deep well region functions as both a source junction in the vertical FET device and a junction barrier region in the integrated bypass diode. The vertical FET device and the integrated bypass diode may include a substrate, a drift layer over the substrate, and a spreading layer over the drift layer, such that the junction implants of the vertical FET device are formed in the spreading layer.

15 kV IGBTs in 4H-SiC

Abstract: The latest developments in ultra high voltage 4H-SiC IGBTs are presented. A 4H-SiC P-IGBT, with a chip size of 8.4 mm x 8.4 mm and an active area of 0.32 cm2, which is double the active area of the previously reported devices [1], exhibited a blocking voltage of 15 kV, while showing a room temperature differential specific on-resistance of 41 mΩ-cm2 with a gate bias of -20 V. A 4H-SiC N-IGBT with the same area showed a blocking voltage of 17 kV, and demonstrated a room temperature differential specific on-resistance of 25.6 mΩ-cm2 with a gate bias of 20 V. Field-Stop buffer layer design was used to control the charge injection from the backside. A comparison between N- and P- IGBTs, and the effects of different buffer designs, are presented.

16 kV, 1 cm2, 4H-SiC PiN Diodes for Advanced High-Power and High-Temperature Applications

Abstract: In this work, we report our recently developed 16 kV, 1 cm2, 4H-SiC PiN diode results. The SiC PiN diode was built on a 120 µm, 2×1014/cm3 doped n-type SiC drift layer with a device active area of 0.5175 cm2. Forward conduction of the PiN diode was characterized at temperatures from 20°C to 200°C. At high injection-current density (JF) of 350 ~ 400 A/cm2, the differential on-resistance (RON,diff) of the SiC PiN diode decreased from 6.08 mΩ·cm2 at 20°C to 5.12 mΩ·cm2 at 200°C, resulting in a very small average temperature coefficient of –5.33 µΩ·cm2/°C, while the forward voltage drop (VF) at 100 A/cm2 reduced from 4.77 V at 20°C to 4.17 V at 200°C. This is due to an increasing high-level carrier lifetime with an increase in temperature, resulting in reduced forward voltage drop. We also observed lower RON,diff at higher injection-current densities, suggesting that a higher carrier lifetime is needed in this lightly doped n-type SiC thick epi-layer in order to achieve full conductivity modulation. The anode to cathode reverse blocking leakage current was measured as 0.9 µA at 16 kV at room temperature.

Layout configurations for integrating schottky contacts into a power transistor device

Abstract: A semiconductor device includes a vertical field-effect-transistor (FET) and a bypass diode. The vertical FET device includes a substrate, a drift layer formed over the substrate, a gate contact and a plurality of source contacts located on a first surface of the drift layer opposite the substrate, a drain contact located on a surface of the substrate opposite the drift layer, and a plurality of junction implants, each of the plurality of junction implants laterally separated from one another on the surface of the drift layer opposite the substrate and extending downward toward the substrate. Each of the one or more bypass diodes are formed by placing a Schottky metal contact on the first surface of the drift layer, such that each Schottky metal contact runs between two of the plurality of junction implants.

Optical Triggering of 12 kV 1 cm2 4H-SiC Thyristors

Abstract: We report on switch-on of 12 kV, 1cm2 optically triggered 4H-SiC thyristor fabricated by CREE Inc., to Imax=270 А with current rise time of ~ 3 s. Temperature dependence of holding current Ih in this thyristor has been experimentally studied in the temperature range from 300 to 425 K. It is shown that measurements of Ih temperature dependence under condition of optical switch-on at small anode bias and large load resistance reveal the existence of a ”weak point” within the optical window. This point is characterized by a much smaller critical charge than that within the remaining part of the window.