J
John W. Palmour
Researcher at Durham University
Publications - 209
Citations - 9172
John W. Palmour is an academic researcher from Durham University. The author has contributed to research in topics: Silicon carbide & Diode. The author has an hindex of 46, co-authored 202 publications receiving 8835 citations. Previous affiliations of John W. Palmour include Cree Inc. & Ioffe Institute.
Papers
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Proceedings ArticleDOI
4.5 kV 60A SICGT and its Half Bridge Inverter Operation of 20kVA Class
Yoshitaka Sugawara,Katsunori Asano,S. Ogata,Anant K. Agarwal,Sei-Hyung Ryu,John W. Palmour,S. Okada,Y. Miyanagi +7 more
TL;DR: In this article, a PWM half bridge inverter was built by using a couple of SICGT modules, which achieved an output power of 20 kVA at V DC of 2kV and carrier frequency of 2kHz, this represents the largest output power among the reported SiC inverters.
Journal ArticleDOI
A 1cm × 1cm, 5kV, 100A, 4H-SiC Thyristor Chip for High Current Modules
Anant K. Agarwal,Sumi Krishnaswami,Ben Damsky,James Richmond,Craig Capell,Sei-Hyung Ryu,John W. Palmour +6 more
TL;DR: In this article, the first 1 cm x 1 cm SiC Thyristor chip capable of blocking 5 kV at 100 A and 25°C has been measured, and the turn-on delay is found to be a strong function of the gate current.
Patent
Carbonized silicon metal-oxide-semiconductor field effect transistor
Ranbir Singh,John W. Palmour +1 more
TL;DR: In this article, a carbonized silicon MOSFET is provided to obtain a breakdown voltage in a forward breakdown mode which is almost similar to the breakdown voltage of a bulk semiconductor.
Journal ArticleDOI
Gate Bias Effects on SiC MOSFET Terrestrial-Neutron Single-Event Burnout
TL;DR: In this article , the effect of negative gate bias, commonly applied during MOSFET switching to the blocking state, on the single-event burnout failure rate was examined, and it was observed that the SEB failure rate is only weakly dependent on the negative-gate bias, because it does not significantly affect the peak field in the drift region where avalanche breakdown is initiated.
Proceedings ArticleDOI
Negative Gate Bias TDDB evaluation of n-Channel SiC Vertical Power MOSFETs
Satyaki Ganguly,Daniel J. Lichtenwalner,Caleb Isaacson,D. A. Gajewski,Philipp Steinmann,Ryan Foarde,Brett Hull,Sei-Hyung Ryu,Scott Allen,John W. Palmour +9 more
TL;DR: In this paper , the negative gate bias TDDB data measured at 175 °C and at a gate oxide electric field of about 4 MV/cm, an intrinsic lifetime of 1E8 hours has been predicted, which closely matches with the results obtained from similar devices under positive gate stress.