Three parallel algorithms for classical molecular dynamics are presented. The first assigns each processor a fixed subset of atoms; the second assigns each a fixed subset of inter-atomic forces to compute; the third assigns each a fixed spatial region. The algorithms are suitable for molecular dynamics models which can be difficult to parallelize efficiently—those with short-range forces where the neighbors of each atom change rapidly. They can be implemented on any distributed-memory parallel machine which allows for message-passing of data between independently executing processors. The algorithms are tested on a standard Lennard-Jones benchmark problem for system sizes ranging from 500 to 100,000,000 atoms on several parallel supercomputers--the nCUBE 2, Intel iPSC/860 and Paragon, and Cray T3D. Comparing the results to the fastest reported vectorized Cray Y-MP and C90 algorithm shows that the current generation of parallel machines is competitive with conventional vector supercomputers even for small problems. For large problems, the spatial algorithm achieves parallel efficiencies of 90% and a 1840-node Intel Paragon performs up to 165 faster than a single Cray C9O processor. Trade-offs between the three algorithms and guidelines for adapting them to more complex molecular dynamics simulations are also discussed.

Fast parallel algorithms for short-range molecular dynamics

다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

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High-κ gate dielectrics: Current status and materials properties considerations

https://dc.engconfintl.org/cgi/viewcontent.cgi?article=1032&context=superalloys_ii

A critical review of high entropy alloys and related concepts

인공고관절의 세라믹 볼 헤드의 기계적 안정성 평가를 위한 3 차원 유한요소 해석

This paper describes an approach for embedding high value, thin film capacitors into high density multilayer printed circuit boards. Pb 0.85 La 0.15 (Zr 0.52 Ti 0.48 ) 0.96 O 3 thin films are prepared by chemical solution deposition on 50 μm Ni-coated Cu foils. Capacitance density and loss tangent values range between 300 and 400 nF/cm 2 and 0.01 and 0.02 from 1 to 1000 kHz respectively. Integration of these foils into a standard HDI process. The capacitance densities represent a 2 to 3 order of magnitude improvement over currently available embedded capacitor technologies for polymeric packages.

Thin film capacitors embedded into high density printed circuit boards

Disclosed are high permittivity (dielectric constant), thin film CSD barium titanate based dielectric compositions that have titanium partially substituted by zirconium, tin or hafnium. The compositions show capacitance as a function of temperature that better satisfies the X7R requirements.

Barium Titanate Thin Films with Titanium Partially Substituted by Zirconium, Tin or Hafnium

The microstructure of polycrystalline barium titanate (BaTiO3) thin films processed with a liquid-phase can be controlled by the crystallographic orientation of the underlying sapphire substrate. During postdeposition crystallization, the tendency for {111} twin nucleation, which drives subsequent abnormal grain growth, depends upon the specific sapphire facet. Specifically, tilting away from the close-packed c-plane modifies the orientation, morphology, and relative amount of an interfacial BaAl2O4 second phase. These factors control the density of twin formation, and thus overall grain size of the crystallized BaTiO3. As the substrate orientation transitions from c-plane, to r-plane, to a-plane, the twin density is reduced, the average grain size decreases systematically from 270 to 130 nm, and the grain structure becomes overall more homogeneous. This twinning mechanism and abnormal grain growth occur by 900°C, several hundred degrees lower than reported previously.

Low‐Temperature Control of Twins and Abnormal Grain Growth in BaTiO3

GaN surface and near-surface chemistry influence on band offsets of oxide overlayers is demonstrated through X-ray photoelectron spectroscopy measurements using epitaxial (111)-oriented MgO films on (0001)-oriented Ga-polar GaN as a case study. For identical cleaning and MgO growth conditions, GaN subsurface oxygen impurities influence the GaN bare surface band bending and the ultimate band offset to MgO heterolayers. As the GaN surface oxygen concentration increases from an atomic concentration of 0.9% to 3.4%, the valence band offset to MgO decreases from 1.68 eV to 1.29 eV, respectively. This study highlights the sensitivity of the oxide/nitride interface electronic structure to GaN epilayer preparation and growth conditions.

Nitride surface chemistry influence on band offsets at epitaxial oxide/GaN interfaces

A process suitable for preparing metal-insulator-metal thin film capacitors with submicron insulating layers and top electrodes with cm-scale dimensions is presented. Most importantly, this process does not require sophisticated deposition equipment or a clean room environment. The key to large area yield is co-firing the insulator film with a non-dewetting electrode during the dielectric crystallization/densification anneal. We propose a mechanism of electrode dewetting during the high temperature anneal where the metal laterally retreats from geometric asperities that compromise the integrity of the insulating layer. This behavior is driven by surface energy minimization, which promotes metal migration away from the regions of high curvature. This methodology is not material specific, and only requires a top electrode with a large contact angle to the dielectric in question. Using this technique, functional thin film capacitors with 2.5 cm lateral dimensions and 1 μm dielectric thicknesses can be routinely prepared.

Jon Paul Maria

Papers

Thin film capacitors embedded into high density printed circuit boards

Barium Titanate Thin Films with Titanium Partially Substituted by Zirconium, Tin or Hafnium

Low‐Temperature Control of Twins and Abnormal Grain Growth in BaTiO3

Nitride surface chemistry influence on band offsets at epitaxial oxide/GaN interfaces

Smart electrodes for ultralarge-area thin film capacitors