Showing papers by "Jose Silva-Martinez published in 2004"

A frequency compensation scheme for LDO voltage regulators

Abstract: A stable low dropout (LDO) voltage regulator topology for low equivalent series resistance (ESR) capacitive loads is presented. The proposed scheme generates a zero internally instead of relying on the zero generated by the load capacitor and its ESR combination for stability. It is demonstrated that this scheme realizes robust frequency compensation, facilitates the use of multilayer ceramic capacitors for the load of LDO regulators, and improves transient response and noise performance. Test results from a prototype fabricated in AMI 0.5-/spl mu/m CMOS technology provide the most important parameters of the regulator viz., ground current, load regulation, line regulation, output noise, and start-up time.

OTA linearity enhancement technique for high frequency applications with IM3 below -65 dB

Abstract: A technique to enhance the linearity of continuous-time operational transconductance amplifiers (OTA)-C filters working at high frequencies is proposed. Each OTA consumes 10.5 mW and the transconductance can be tuned from 70 to 160 /spl mu/A/V while the IM3 remains below -70 dB up to 50 MHz for a 1.3-V/sub pp/ differential input. For a 20-MHz low-pass second-order filter implementation, the measured IM3 with an input voltage of 1.3 V/sub pp/ is below - 65 dB. The supply voltage is 3.3 V. Experimental results of the circuit, fabricated in a standard CMOS 0.35-/spl mu/m technology, are presented.

An on-chip transfer function characterization system for analog built-in testing

Abstract: A compact system for the on-chip transfer function characterization of an analog circuit is presented. It consists of a phase and amplitude detector and a signal generator. A general methodology for the use of this structure in the functional verification of a circuit under test (CUT) is provided. An integrated implementation of the proposed system in CMOS 0.35 /spl mu/m technology is described along with circuit-level design considerations. Experimental results of the application of this system in the characterization of a commercial programmable gain amplifier for frequencies up to 160 MHz are also presented.

Bandwidth enhancement of multi-stage amplifiers using active feedback

Abstract: A new topology for wideband multistage amplifiers (MA) is introduced. The proposed method uses active negative feedback in a chain of amplifiers to extend the bandwidth and improve gain-bandwidth product. The topology has several advantages such as having capability of widening bandwidth as the number of stage increases and enhancing bandwidth by several times that of the dominant pole of each stage. To verify the performance of topology, an 8-stage amplifier in 0.35 /spl mu/m CMOS was designed, where more than 2.8 GHz bandwidth and 40 dB gain were obtained from simulations.

A 500 MHz OTA-C 4/sup th/ order lowpass filter with class AB CMFB in 0.35 /spl mu/m CMOS technology

Abstract: A 500 MHz linear phase low-pass continuous-time filter is designed. A common-mode feedback (CMFB), based on a class AB amplifier with improved stability at high frequencies, is introduced. The filter is based on G/sub m/-C biquads and achieves IM3<-40 dB for a two-tone input signal of -10 dBm each. The power consumption of the 4/sup th/ order filter is 140 mW from supply voltages of +/- 1.65 V. The chip was fabricated in a standard 0.35 /spl mu/m CMOS technology.

6.8 mW 2.5 Gb/s and 42.5 mW 5 Gb/s 1:8 CMOS demultiplexers

Abstract: This paper presents two low-power demultiplexers working at 25 Gbps and 5 Gbps input data rate respectively The 25 Gbps demultiplexer consumes only 68 mW power dissipation The 5 Gbps demultiplexer consumes 425 mW power dissipation The two demultiplexers are implemented in TSMC 035 /spl mu/m CMOS technology They are built on the same chip sharing input and output ports The power supply of the chip is 25 V The demultiplexers are designed to be modules for optical communication receiver systems