This paper presents an overview of the fundamentals and state of the-art in noninvasive physiological monitoring instrumentation with a focus on electrode and optrode interfaces to the body, and micropower-integrated circuit design for unobtrusive wearable applications. Since the electrode/optrode-body interface is a performance limiting factor in noninvasive monitoring systems, practical interface configurations are offered for biopotential acquisition, electrode-tissue impedance measurement, and optical biosignal sensing. A systematic approach to instrumentation amplifier (IA) design using CMOS transistors operating in weak inversion is shown to offer high energy and noise efficiency. Practical methodologies to obviate 1/f noise, counteract electrode offset drift, improve common-mode rejection ratio, and obtain subhertz high-pass cutoff are illustrated with a survey of the state-of-the-art IAs. Furthermore, fundamental principles and state-of-the-art technologies for electrode-tissue impedance measurement, photoplethysmography, functional near-infrared spectroscopy, and signal coding and quantization are reviewed, with additional guidelines for overall power management including wireless transmission. Examples are presented of practical dry-contact and noncontact cardiac, respiratory, muscle and brain monitoring systems, and their clinical applications.

Integrated Circuits and Electrode Interfaces for Noninvasive Physiological Monitoring

This paper presents an analog-to-digital converter (ADC) dedicated to neural recording systems. By using two continuous-time incremental sigma-delta ADCs in a pipeline configuration, the proposed ADC can achieve high-resolution without sacrificing the conversion rate. This two-step architecture is also power-efficient, as the resolution requirement for the incremental sigma-delta ADC in each step is significantly relaxed. To further enhance the power efficiency, a class-AB output stage and a dynamic summing comparator are used to implement the sigma-delta modulators. A prototype chip, designed and fabricated in a standard 0.18 $\mu{\rm m}$ CMOS process, validates the proposed ADC architecture. Measurement results show that the ADC achieves a peak signal-to-noise-plus-distortion ratio of 75.9 dB over a 4 kHz bandwidth; the power consumption is 34.8 $\mu{\rm W}$ , which corresponds to a figure-of-merit of 0.85 pJ/conv.

/pdf/a-power-efficient-continuous-time-incremental-sigma-delta-2ps5ljce4i.pdf

A Power-Efficient Continuous-Time Incremental Sigma-Delta ADC for Neural Recording Systems

This paper proposes a 3 rd order single-loop continuous-time incremental sigma-delta analogue-to-digital con- verter (ADC) for time-multiplexed signals. Incremental sigma- delta modulation is used to address medium to high resolution requirements of multi-channel applications, while a 3 rd order continuous-time implementation is investigated as an alternative for low-power solutions. A prototype of the proposed modulator, running at 320 kHz, has been fabricated in a 0.15-µm CMOS technology, while the synchronization circuitry to allow incre- mental operation was built on-board. Measurement results show that the ADC achieves 65.3 dB peak SNR, 64 dB peak SNDR and 68.2 dB dynamic range over a 2 kHz bandwidth. The modulator's power dissipation is 96 µW from a 1.6 V power supply. This translates into the best figure-of-merit when compared to recently published continuous-time alternatives, while being competitive with respect to state-of-the-art discrete-time counterparts. Index Terms—A/D conversion, incremental ADC, continuous-time.

A Low-Power CT Incremental 3rd Order ΣΔ ADC for Biosensor Applications.

This paper describes a capacitive touch-screen panel (TSP) readout IC that provides a reconfigurable SNR and frame rate with high noise immunity and touch sensitivity. The readout IC mitigates severe noise interference with a lock-in sensing architecture. In addition, a band-pass filtering effect by the TSP and charge amplifier further improves the noise immunity. A differential sensing scheme is employed to enhance the touch sensitivity and to reject a common-mode noise. A column-parallel incremental ΣΔ ADC is adopted to provide a high resolution and frame rate. Furthermore, a multiple sampling and averaging effect of the ADC enhances the noise immunity. The readout IC reconfigures its SNR and frame rate by adjusting the configurable resolution of the employed ADC. The test chip is fabricated in a 0.18 μm CMOS process and occupies a 2.2 mm 2 active area. The test chip achieves a 60 dB SNR and 200 Hz frame rate with a 12×8 TSP. The SNR can be adjusted from 40 dB to 67 dB, while the frame rate is then inversely scaled from 50 Hz to 6.4 kHz. The test chip supports a supply voltage range from 2.1 V to 3.3 V and consumes 6.26 mW from a 3.3 V supply.

A Reconfigurable 40-to-67 dB SNR, 50-to-6400 Hz Frame-Rate, Column-Parallel Readout IC for Capacitive Touch-Screen Panels

This paper presents an integrated circuit (IC) that merges integrated optical and temperature transducers, optical interface circuitry, and a near-field communication (NFC)-enabled digital, wireless readout for a fully passive implantable sensor platform to measure glucose in people with diabetes. A flip-chip mounted LED and monolithically integrated photodiodes serve as the transduction front-end to enable fluorescence readout. A wide-range programmable transimpedance amplifier adapts the sensor signals to the input of an 11-bit analog-to-digital converter digitizing the measurements. Measurement readout is enabled by means of wireless backscatter modulation to a remote NFC reader. The system is able to resolve current levels of less than 10 pA with a single fluorescent measurement energy consumption of less than 1 μJ. The wireless IC is fabricated in a 0.6-μm-CMOS process and utilizes a 13.56-MHz-based ISO15693 for passive wireless readout through a NFC interface. The IC is utilized as the core interface to a fluorescent, glucose transducer to enable a fully implantable sensor-based continuous glucose monitoring system.

An NFC-Enabled CMOS IC for a Wireless Fully Implantable Glucose Sensor

This paper proposes a 3rd order single-loop continuous-time incremental sigma-delta analogue-to-digital converter (ADC) for time-multiplexed signals. Incremental sigma-delta modulation is used to address medium to high resolution requirements of multi-channel applications, while a 3rd order continuous-time implementation is investigated as an alternative for low-power solutions. A prototype of the proposed modulator, running at 320 kHz, has been fabricated in a 0.15-μm CMOS technology, while the synchronization circuitry to allow incremental operation was built on-board. Measurement results show that the ADC achieves 65.3 dB peak SNR, 64 dB peak SNDR and 68.2 dB dynamic range over a 2 kHz bandwidth. The modulator's power dissipation is 96 μW from a 1.6 V power supply. This translates into the best figure-of-merit when compared to recently published continuous-time alternatives, while being competitive with respect to state-of-the-art discrete-time counterparts.

/pdf/a-low-power-ct-incremental-3rd-order-spl-sigma-spl-delta-adc-1pzmpn3b0f.pdf

A Low-Power CT Incremental 3rd Order /spl Sigma//spl Delta/ ADC for Biosensor Applications

A novel built-in self calibration technique for single-loop continuous-time sigma-delta modulators is proposed. Using out-of-band test signal injection and digital cancellation, this technique provides an area efficient, highly digital calibration structure to counteract gain variations in the loop filter. The calibration methodology and mathematical analysis are presented using a 2nd order multibit sigma-delta modulator as a proof of concept. The effect of the finite gain-bandwidth of amplifiers is included when evaluating the calibration method. The proposed technique is validated through corner simulations using behavioral models and it shows that degradation in the signal-to-noise-plus-distortion ratio can be counteracted.

/pdf/built-in-self-calibration-for-process-variation-in-single-1dd1b43o3g.pdf

Built-in self calibration for process variation in single-loop continuous-time sigma-delta modulators

In this paper, the use of continuous-time implementation in extended-range (ER) incremental sigma-delta analog-to-digital converters is analyzed in order to explore a possible solution to low-power multichannel applications. The operation principle, possible loop filter topologies, and critical issues are considered using a general approach. It is demonstrated that, in order to fully benefit from ER, careful attention has to be paid to the analog-digital transfer function mismatches. A third-order single-bit topology validates the theoretical analysis. Its performance is evaluated while the impact of key circuit nonidealities is quantified through behavioral-level simulations. It is shown that, by applying analog-digital mismatch compensation in the digital domain, it is possible to relax the amplifiers' finite gain-bandwidth product and finite dc gain requirements, thus allowing a power-conscious alternative.

/pdf/on-continuous-time-incremental-sigma-delta-adcs-with-j7j2eornk8.pdf

On Continuous-Time Incremental $\Sigma\Delta$ ADCs With Extended Range

A novel high-order single-loop incremental sigma-delta ADC for multi-channel applications is proposed. High-order continuous-time architectures are explored using a 3rd order single-bit modulator as a test-case. The performance of the proposed architecture, taking into account critical non-idealities, is analyzed and its advantages and issues are discussed. Behavioral simulations show a key advantage regarding the integrators' gain-bandwidth requirement of the proposed ADC compared to discrete-time counterparts. This advantage leads to possible low power solutions for multi-channel applications.

/pdf/high-order-continuous-time-incremental-sd-adc-for-multi-52vp2zr60x.pdf

Julian Garcia

Papers

A Low-Power CT Incremental 3rd Order ΣΔ ADC for Biosensor Applications.

A Low-Power CT Incremental 3rd Order /spl Sigma//spl Delta/ ADC for Biosensor Applications

Built-in self calibration for process variation in single-loop continuous-time sigma-delta modulators

On Continuous-Time Incremental $\Sigma\Delta$ ADCs With Extended Range

High-order continuous-time incremental ΣΔ ADC for multi-channel applications