Jung-Hwan Choi

TL;DR: A DRAM interface operating at 3.6 Gb/s/pin implemented in 130-nm CMOS logic and 110-nm DRAM process technologies utilizes simultaneous bidirectional signaling in a daisy-chained, point-to-point configuration to enable high performance scalable memory subsystems and also provides direct attach capability for DRAMs to memory controllers or other logic devices.

TL;DR: Dual error detection scheme is proposed to guarantee the reliability of signals, and gain enhanced buffer and PVT tolerant data fetch scheme are adopted for CA and DQ respectively to reduce the output jitter.

TL;DR: A point-to-point I/O interface for high-speed DRAM that utilizes simultaneous bidirectional signaling that enables transmitting/receiving data through a line at the same time is described.

TL;DR: The 2nd generation HBM is proposed to double the bandwidth to more than 256GB/s and support pseudo-channel mode and 8H stacks, and an adaptive refresh considering temperature distribution (ART) scheme as a solution.

TL;DR: A 4Gb DDR3 SDRAM that supports a 1.2V supply voltage and 1.6Gb/s data rate to address the growing need for data bandwidth and capacity in computer systems.