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Byung-Hyun Lee
Researcher at KAIST
Publications - 51
Citations - 757
Byung-Hyun Lee is an academic researcher from KAIST. The author has contributed to research in topics: Transistor & Field-effect transistor. The author has an hindex of 14, co-authored 51 publications receiving 614 citations. Previous affiliations of Byung-Hyun Lee include Samsung.
Papers
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Journal ArticleDOI
Direct Observation of a Carbon Filament in Water-Resistant Organic Memory.
Byung-Hyun Lee,Hagyoul Bae,Hyejeong Seong,Dongil Lee,Hongkeun Park,Young Joo Choi,Sung Gap Im,Sang Ouk Kim,Yang-Kyu Choi +8 more
TL;DR: iCVD polymer-intercalated RRAM (i-RRAM) is demonstrated, which is the first experimental presentation of water-resistant organic memory without any waterproof protection package and the direct observation of a carbon filament is reported for the first time using transmission electron microscopy, putting an end to the controversy surrounding the switching mechanism.
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Comprehensive Analysis of Gate-Induced Drain Leakage in Vertically Stacked Nanowire FETs: Inversion-Mode Versus Junctionless Mode
TL;DR: In this paper, the gate-induced drain leakage (GIDL) current of vertically stacked nanowire (VS-NW) FETs was analyzed, and two different operational modes of the VS-NW, an inversion mode (IM) and a junctionless mode (JM), were compared.
Journal ArticleDOI
A Vertically Integrated Junctionless Nanowire Transistor
Byung-Hyun Lee,Byung-Hyun Lee,Jae Hur,Minho Kang,Tewook Bang,Dae-Chul Ahn,Dongil Lee,Kwang-Hee Kim,Yang-Kyu Choi +8 more
TL;DR: The proposed VJ-FET mitigates the issues of variability and fabrication complexity that are encountered in the vertically integrated multi-NW FET based on an identical structure and the endurance and retention characteristics are improved due to the above-mentioned bulk conduction.
Journal ArticleDOI
Vertically Integrated Multiple Nanowire Field Effect Transistor.
Byung-Hyun Lee,Byung-Hyun Lee,Minho Kang,Dae-Chul Ahn,Jun-Young Park,Tewook Bang,Seung-Bae Jeon,Jae Hur,Dongil Lee,Yang-Kyu Choi +9 more
TL;DR: This research suggests an ultimate design for the end-of-the-roadmap devices to overcome the limits of scaling and is revamped to create nonvolatile memory with the adoption of a charge trapping layer for enhanced practicality.
Journal ArticleDOI
A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme
Kyomin Sohn,Taesik Na,In-Dal Song,Yong Shim,Won-Il Bae,Sang-Hee Kang,Dong Su Lee,Han-Gyun Jung,Hanki Jeoung,Ki-Won Lee,Junsuk Park,Jongeun Lee,Byung-Hyun Lee,Inwoo Jun,Ju-Seop Park,Junghwan Park,Hundai Choi,Sang Hee Kim,Haeyoung Chung,Young Sang Choi,Dae-Hee Jung,Jang Seok Choi,Byung-sick Moon,Jung-Hwan Choi,Byung-Chul Kim,Seong-Jin Jang,Joo Sun Choi,Kyung Seok Oh +27 more
TL;DR: Dual error detection scheme is proposed to guarantee the reliability of signals, and gain enhanced buffer and PVT tolerant data fetch scheme are adopted for CA and DQ respectively to reduce the output jitter.