A method to determine the small-signal equivalent circuit of FETs is proposed This method consists of a direct determination of both the extrinsic and intrinsic small-signal parameters in a low-frequency band This method is fast and accurate, and the determined equivalent circuit fits the S-parameters well up to 265 GHz >

A new method for determining the FET small-signal equivalent circuit

The physical basis of the cold-FET method for extracting parasitic resistances and inductances is examined. A method to obtain the source resistance from the gate-current dependence of the FET Z parameters is used to analyze FETs with different gate lengths. Inductance results for FETs with different gate widths suggest that inductance extrinsic to the gate fingers is dominant, and models of the gate inductance support this. The effects that possible dependences of the parasitic-FET equivalent-circuit parameters (ECPs) on the gate and drain bias can have on the extracted intrinsic-FET parameters are discussed. >

Equivalent-circuit parameter extraction for cold GaAs MESFET's

A programmable input/output device for use with a programmable logic device (PLD) is presented comprising an input buffer, an output buffer and programmable elements. The programmable elements may be programmed to select a logic standard for the input/output device to operate at. For instance, a given set of Select Bits applied to the programmable elements may select TTL logic, in which case the input and output buffers would operate according to the voltage levels appropriate for TTL logic (e.g., 0.4 volts to 2.4 volts). For a different set of Select Bits, the GTL logic standard would be applied (e.g., 0.8 volts to 1.2 volts). The invention enables a single PLD to be used in conjunction with various types of external circuitry.

System for coupling programmable logic device to external circuitry which selects a logic standard and uses buffers to modify output and input signals accordingly

S-parameters of MODFETs were measured versus bias instead of frequency with a special feature of the HP8510 network analyzer. Figure of merit plots, f/sub T/, and f/sub max/, were quickly generated from the bias sweeps of S-parameters, and optimum bias points were easily found. The intrinsic device elements of MODFETs were calculated after de-embedding the measurements from the device parasitics. The technique is demonstrated with a 0.15- mu m pseudomorphic MODFET with an f/sub T/ of 150 GHz. The usefulness of the technique for understanding the operation of the MODFETs is discussed. With this technique a bias scan of an intrinsic element value can be measured and plotted in 13 s. >

Bias dependence of the MODFET intrinsic model elements values at microwave frequencies

A novel and accurate analytical direct extraction method for the determination of MESFET and HEMT parasitic elements is described. The technique differs from the commonly used "cold-FET" technique by avoiding the forward biasing of the Schottky gate junction. The parasitic capacitances, inductances and resistances are directly extracted from S-parameter measurements under pinched-FET and zero-bias conditions. Ambiguities commonly observed during resistance extraction using cold-FET techniques are avoided with the new method.

A new and reliable direct parasitic extraction method for MESFETs and HEMTs

Techniques which allow us to determine the series source, drain, and gate resistances and the electron saturation velocity of ion-implanted GaAs FET's are described. These techniques are based on the "end" resistance measurements. The theory of this method is developed and used for a new interpretation of the "end" resistance measurements. The values of the series resistances determined by this technique are shown to be in an excellent agreement with those obtained by the modified Fukui method. The values of the electron saturation velocity varying from 1.0 × 105m/s to 1.3 × 105m/s are obtained using the end resistance method. The proposed set of measurements is simple and accurate enough to be used as a routine characterization technique for GaAs FET's.

Source, drain, and gate series resistances and electron saturation velocity in ion-implanted GaAs FET's

We develop a model which describes the current-voltage characteristics of GaAs saturated resistor loads (or ungated FET's) with uniform and nonuniform (ion-implanted) doping profiles The results of the calculation are in good agreement with the experimental data for 1-, 2-, and 3-µm GaAs ungated FET's Our model allows us to determine the values of the electron saturation velocity ν s and of the surface built-in voltage V Sbi from the measured current-voltage characteristics of ungated loads For long devices (with 3-µm length) we obtain \nu_{s} \approx 120-121 \times 10^{5} m/s and V_{Sbi} \approx 046-047 V, in good agreement with expected values For shorter (1 µm) devices, the measured values of ν s are considerably higher (164-173 × 105m/s) This may be considered as evidence of velocity enhancement in short structures due to ballistic or overshoot effects

Current&#8212;Voltage characteristics of ungated GaAs FET's

Describes a GaAs gate array with on-chip RAM based on the Schottky diode field-effect transistor logic (SDFL) technology. The array features 432 programmable SDFL cells, 32 programmable interface input-output (I/O) buffers, and four 4/spl times/4 bit static random access memories (RAM) on a 147 mil/spl times/185 mil chip. Each SDFL cell can be programmed as a NOR gate with as many as 8 inputs with a buffered or unbuffered output or as a dual OR-NAND gate with four inputs per side. The interface I/O buffer can be programmed for ECL, TTL, CMOS, and SDFL logic families. Each 4/spl times/4 bit RAM is fully decoded using SDFL circuits (depletion-mode MESFET). Preliminary results demonstrate the feasibility of GaAs SDFL for fast gate array and memory applications.

A gallium arsenide SDFL gate array with on-chip RAM

Parameters of a DCFL inverter, such as propagation delay, inverter gain, switching voltage, output voltage levels and noise margins, are related (in an analytical form) to the parameters of the switching transistor and load transistor, such as the load saturation current, the switching transistor threshold voltage, the load and switching transistor output conductances, etc., and to the gate fan-in and fan-out. The results demonstrate tradeoffs between the noise margins, propagation delay and power consumption and are in reasonable agreement with experimental data for GaAs self-aligned inverters and with the results of circuit simulation of DCFL inverters and ring oscillators.

Design Analysis of GaAs Direct Coupled Field Effect Transistor Logic

An OR logic function is provided in at least two separate circuit branches by diodes in parallel summing current at a first logic node and a first circuit branch and diodes in parallel summing current at a second logic node in a second current branch. An AND logic function is performed at a third logic node by using additional diodes connected in parallel at the third logic node so as to share current passing through the third logic node, with the logic conditions at the first and second logic nodes serving as the inputs to the AND logic function. The logic condition at the third logic node is applied to the gate of a switching FET. The switching FET is conveniently employed to invert the logic condition at the third logic node. The invention is particularly suited for use with MESFET logic families using gallium arsenide (GaAs) substrates.

K.W. Lee

Papers

Source, drain, and gate series resistances and electron saturation velocity in ion-implanted GaAs FET's

Current—Voltage characteristics of ungated GaAs FET's

A gallium arsenide SDFL gate array with on-chip RAM

Design Analysis of GaAs Direct Coupled Field Effect Transistor Logic

Multiple input and multiple output or/and circuit

K.W. Lee

Papers

Source, drain, and gate series resistances and electron saturation velocity in ion-implanted GaAs FET's

Current&#8212;Voltage characteristics of ungated GaAs FET's

A gallium arsenide SDFL gate array with on-chip RAM

Design Analysis of GaAs Direct Coupled Field Effect Transistor Logic

Multiple input and multiple output or/and circuit

Current—Voltage characteristics of ungated GaAs FET's