A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s.

Asymmetric dense floating gate nonvolatile memory with decoupled capacitor

This brief proposes a new 45-nm erasable one-time programming cell with a self-aligned nitride (SAN) storage node for logic nonvolatile memory (NVM) applications. The CMOS fully logic-compatible cell was successfully demonstrated using 45-nm CMOS technology with a very small cell size of 0.1188 mum2. This cell-adapting source-side-injection programming scheme has a wide on/off window and superior program efficiency. The SAN cell with five terminals for various operational conditions uses an asymmetrical read voltage to verify the position of the stored charge. This cell also exhibits excellent data retention capability even when the thickness of the logic gate oxide is less than 20 A, and the gate length is shorter than 40 nm. This new cell provides a promising solution for logic NVM beyond a 90-nm node.

A Study of Self-Aligned Nitride Erasable OTP Cell by 45-nm CMOS Fully Compatible Process

A new saw-like self-recovery Self-Aligned Nitride (SAN) memory cell is proposed and fabricated in 28nm high-k metal gate (HKMG) CMOS process for high-density logic NVM applications. The cell is operated with Source-Side Injection (SSI) for programming and band-to-band hot holes (BBHH) for erasing. Two effective self-heating recovery mechanisms are proposed and performed to maintain a stable On/Off read window after cycling stresses. Besides, the characteristic and reliability comparison of the SAN cell in other technology nodes, 90nm/45nm/32nm, are characterized to further verify the saw-like self-detrapping and self-recovery operation. The new 28nm HKMG SAN memory cell with the self-detrapping recovery results excellent and superior endurance performance and can provide a very promising solution for logic NVM in advanced technologies.

A new saw-like self-recovery of interface states in nitride-based memory cell

A 32nm MTP cell with a nitride-based storage node using 32nm strained Si process are demonstrated with an ultra small cell size of 0.0528µm2 by a 32nm strained-CMOS fully logic compatible process. A self-aligned tiny nitride storage node is placed in the narrow spacing of two 32nm transistors by a merged transistor spacer mingled with a strained nitride of 32nm strained Si process. The twin-gate cell uses the source side injection (SSI) to obtain 100 times of on/off window by a low program voltage of 3.5V within 1msec. A good reliability in retention and disturb is exhibited due to the inherently decoupling of storage node and transistor gate oxide in this cell, even when gate oxide is thinner than 16A with 32nm gate length only.

32nm strained nitride MTP cell by fully CMOS logic compatible process

This paper reports a new static RAM (SRAM) cell featuring its self-matching characteristic for enhanced static noise margin (SNM) in low-voltage applications. This new SRAM employs trimming devices replacing pull-down transistors to compensate mismatches. Through a blanket trimming operation enabling self-matching of the two branches, effective suppression of variability with improved SNM distribution has been successfully demonstrated in nanoscaled SRAMs.

Self-Matching SRAM With Embedded OTP Cells in Nanoscale Logic CMOS Technologies

A new p-channel nitride-based one-time programmable (OTP) memory was developed for advanced-logic nonvolatile-memory (NVM) applications. A 0.296-mum2/bit (~35 F2) OTP cell, i.e., 0.592 mum2/cell, with a self-aligned nitride storage node was fabricated using standard 90-nm CMOS processes and is fully independent of gate oxide for high scalability. Additionally, the ultrahigh-density OTP cell exhibits excellent retention, immunity against disturbance, and a wide on/off window under the band-to-band hot electron programming. In summary, the new p-channel OTP cell is a very promising solution for use in high-density logic NVM applications beyond the 90-nm technology node.

K. Wu

Papers

A Novel 2-Bit/Cell p-Channel Logic Programmable Cell With Pure 90-nm CMOS Technology