Decreasing read cell current (ICELL) has become a major trend in nonvolatile memory (NVM). However, a reduced ICELL leaves the operation of the sense amplifier (SAs) vulnerable to bitline (BL) level offset and SA input offset. Thus, small- ICELL NVMs suffer from slow read speed or low read yield. In this study, we propose a new current-sampling-based SA (CSB-SA) to suppress the offset due to device mismatch, while maintaining tolerance for insufficient precharge time. These features enable CSB-SA to achieve a read speed 6.3 ×-8.1× faster than previous SAs, for sensing 100 nA ICELLs on a 2 K-cell bitline. We fabricated a CMOS-logic-compatible, 90 nm, 512 Kb OTP macro, using the CSB-SA. This OTP macro achieves a random access time of 26 ns for reading sub-200 nA ICELL. Measurements confirm that this 90 nm CSB-SA is also capable of sub-100 nA sensing.

An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory

Decreasing read cell current (I CELL ) has become a key trend in nonvolatile memory (NVM). This is not only due to device size and V DD scaling while keeping the same threshold voltage (V TH ), but also to the growing spread of the following applications: 1) multiple-level-cell (MLC) [1–2] to achieve smaller area-per-bit; 2) lower-V DD [3] to save power consumption; 3) Logic-process-compatible onetime programming memories (OTP) for embedding into mobile chips. A smaller I CELL leaves the sense amplifiers (SAs) operation vulnerable to 1) bitline (BL) level offset due to noise, bias and load (C BL ) mismatches and 2) V TH variation. As device size and BL-pitch is continually scaled down, the above factors have become major showstopper for SAs. To tolerate these offsets, small-I CELL NVMs suffer from slow read speed or high read fail probability. Thus, a more largely offset tolerant SA is a prerequisite to achieve faster read speeds. In this study, we propose a new offset tolerant current-sampling-based SA (CSB-SA) to achieve 7× faster read speed than previous SAs for sensing small I CELL . A fabricated 90nm 512Kb OTP macro, using the CSB-SA and our CMOS-logic-compatible OTP cell [4], achieves 26ns macro random access time for reading sub-200nA I CELL . Measurements also confirmed that this 90nm CSB-SA could achieve sub-100nA sensing.

An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory

A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s.

Asymmetric dense floating gate nonvolatile memory with decoupled capacitor

We propose a novel 4-bit self-aligned SONOS-type nonvolatile memory (NVM) cell with a T-gate and I-shaped FinFET structure for practical implementation with high storage density and better reliability. In order to obtain enhanced reliability characteristics, a modified Fowler-Nordheim tunneling mechanism is employed for programming along the channel length direction, while a band-to-band hot hole injection is used for erasing along the channel width direction. With separated paths for program and erase, improved device performance is obtained with sensing margin. In order to improve the immunity to second-bit effects, the gate-induced drain leakage current method, which is a charge detection method and highly sensitive to the locally stored charges, is employed for the reading of the stored data. In terms of the scalability, we confirmed by 2-D technology computer-aided design simulation that the proposed NVM cell with channel length L = 50 nm operates with enough sensing margin and high-density ( ~ 5 F2/bit) NVM by the crossed cell array architecture.

/pdf/a-novel-self-aligned-4-bit-sonos-type-nonvolatile-memory-1io5nfgjnz.pdf

A Novel Self-Aligned 4-Bit SONOS-Type Nonvolatile Memory Cell With T-Gate and I-Shaped FinFET Structure

This letter presents a novel differential p-channel logic-compatible multiple-time programmable (MTP) memory cell. This MTP cell has a pair of floating gates, and performs differential read to increase the on/off window. Additionally, a novel self-recovery operation is implemented to boost the floating gate level, thus avoiding the charge-loss problem due to the thin gate oxide requirement in advance logic nonvolatile memory applications. This differential cell with its self-recovery operation is a very promising MTP solution for gate oxide layer with a 70 A thickness, and can be implemented by 3.3 V I/O in 90 nm and the advanced CMOS logic processes such as 45 nm and beyond.

A New Differential P-Channel Logic-Compatible Multiple-Time Programmable (MTP) Memory Cell With Self-Recovery Operation

series withaself-aligned nitride storage nodeformed bythe A new45nmMultiple TimeProgramming (MTP) cell with twomerged nitride spacers asillustrated inFig. 1. self-aligned nitride storage nodehasbeenproposed forlogic NVM applications. TheCMOS fully logic compatible cell has MtlLn beensuccessfully demonstrated in45nmCMOS technology withanultra small cell sizeof0.14Lm2 . Thiscelladapting sourcesideinjection programming scheme hasawideon/off windowandsuperior program efficiency. Anditalso exhibits excellent data retention capability evenwhenlogic gate oxide isless than20Awith45nmgate length. This newcell provides apromising solution forlogic NVM beyond 90nmnode.

http://ieeexplore.ieee.org/iel5/4418847/4418848/04418871.pdf

A NewSelf-Aligned Nitride MTP Cellwith45nmCMOS Fully Compatible Process

A new 45 nm multiple time programming (MTP) cell with self-aligned nitride storage node has been proposed for logic NVM applications. The CMOS fully logic compatible cell has been successfully demonstrated in 45 nm CMOS technology with an ultra small cell size of 0.14 mum2. This cell adapting source side injection programming scheme has a wide on/off window and superior program efficiency. And it also exhibits excellent data retention capability even when logic gate oxide is less than 20 Aring with 45 nm gate length. This new cell provides a promising solution for logic NVM beyond 90 nm node.

A New Self-Aligned Nitride MTP Cell with 45nm CMOS Fully Compatible Process

This brief proposes a new 45-nm erasable one-time programming cell with a self-aligned nitride (SAN) storage node for logic nonvolatile memory (NVM) applications. The CMOS fully logic-compatible cell was successfully demonstrated using 45-nm CMOS technology with a very small cell size of 0.1188 mum2. This cell-adapting source-side-injection programming scheme has a wide on/off window and superior program efficiency. The SAN cell with five terminals for various operational conditions uses an asymmetrical read voltage to verify the position of the stored charge. This cell also exhibits excellent data retention capability even when the thickness of the logic gate oxide is less than 20 A, and the gate length is shorter than 40 nm. This new cell provides a promising solution for logic NVM beyond a 90-nm node.

A Study of Self-Aligned Nitride Erasable OTP Cell by 45-nm CMOS Fully Compatible Process

A new p-channel nitride-based one-time programmable (OTP) memory was developed for advanced-logic nonvolatile-memory (NVM) applications. A 0.296-mum2/bit (~35 F2) OTP cell, i.e., 0.592 mum2/cell, with a self-aligned nitride storage node was fabricated using standard 90-nm CMOS processes and is fully independent of gate oxide for high scalability. Additionally, the ultrahigh-density OTP cell exhibits excellent retention, immunity against disturbance, and a wide on/off window under the band-to-band hot electron programming. In summary, the new p-channel OTP cell is a very promising solution for use in high-density logic NVM applications beyond the 90-nm technology node.

A Novel 2-Bit/Cell p-Channel Logic Programmable Cell With Pure 90-nm CMOS Technology

This study demonstrates a logic compatible p-channel self-aligned-nitride (SAN) cell for one-time programming (OTP) memory applications. The SAN storage structure is independent of the gate oxide thickness, allowing these cells to be performed in a pure advanced logic process beyond 90 nm. The study also exams the characteristics of the source-side injection hot electron (SSIHE) scheme using the simulation tools, and successfully verified the programming characteristics of the p-channel SAN cell with different program voltages. Moreover, this study shows the proposed SAN cell has a wide read current window, high reliability, and superior immunity to disturbance. Combined with a source-side injection scheme, this cell provides a promising solution for advanced logic nonvolatile memory (NVM) applications.

Ying-Je Chen

Papers

A NewSelf-Aligned Nitride MTP Cellwith45nmCMOS Fully Compatible Process

A New Self-Aligned Nitride MTP Cell with 45nm CMOS Fully Compatible Process

A Study of Self-Aligned Nitride Erasable OTP Cell by 45-nm CMOS Fully Compatible Process

A Novel 2-Bit/Cell p-Channel Logic Programmable Cell With Pure 90-nm CMOS Technology

Source Side Injection Programmed P-Channel Self-Aligned-Nitride One-Time Programming Cell for 90 nm Logic Nonvolatile Memory Applications